Cypress CY62136EV30 manual Document History, REV ECN no, Issue Date Orig. Description of Change

Page 12

CY62136EV30

MoBL®

Document History Page

Document Title: CY62136EV30 MoBL® 2-Mbit (128K x 16) Static RAM

Document Number: 38-05569

REV.

ECN NO.

Issue Date

Orig. of

Description of Change

Change

 

 

 

 

 

**

237432

See ECN

AJU

New Data Sheet

 

 

 

 

 

*A

419988

See ECN

RXU

Converted from Advanced Information to Final.

 

 

 

 

Changed the address of Cypress Semiconductor Corporation on Page #1

 

 

 

 

from “3901 North First Street” to “198 Champion Court”

 

 

 

 

Removed 35ns Speed Bin

 

 

 

 

Removed “L” version of CY62136EV30

 

 

 

 

Changed ICC (Max) value from 2 mA to 2.5 mA and ICC (Typ) value from

 

 

 

 

1.5 mA to 2 mA at f=1 MHz

 

 

 

 

Changed ICC (Typ) value from 12 mA to 15 mA at f = fmax

 

 

 

 

Changed ISB1 and ISB2 Typ. values from 0.7 A to 1 A and Max. values from

 

 

 

 

2.5 A to 7 A.

 

 

 

 

Changed the AC test load capacitance from 50pF to 30pF on Page# 4

 

 

 

 

Changed VDR from 1.5V to 1V on Page# 4.

 

 

 

 

Changed ICCDR from 2.5 A to 3 A.

 

 

 

 

Added ICCDR typical value.

 

 

 

 

Changed tOHA , tLZCE and tLZWE from 6 ns to 10 ns

 

 

 

 

Changed tLZBE from 6 ns to 5 ns

 

 

 

 

Changed tLZOE from 3 ns to 5 ns

 

 

 

 

Changed tHZOE, tHZCE, tHZBE and tHZWE from 15 ns to 18 ns

 

 

 

 

Changed tSCE,tAW and tBW from 40 ns to 35 ns

 

 

 

 

Changed tPWE from 30 ns to 35 ns

 

 

 

 

Changed tSD from 20 ns to 25 ns

 

 

 

 

Corrected typo in the Truth Table on Page# 9

 

 

 

 

Updated the package diagram 48-pin VFBGA from *B to *D

 

 

 

 

Updated the ordering Information table and replaced the Package Name

 

 

 

 

column with Package Diagram.

*B

427817

See ECN

NXR

Minor change: Moved datasheet to external web

 

 

 

 

 

Document #: 38-05569 Rev. *B

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Contents Features Logic Block DiagramCypress Semiconductor Corporation Pin Configuration2 Product Portfolio4Vfbga Top View Tsop II Top View MaxElectrical Characteristics Over the Operating Range 5, 6 Maximum RatingsOperating Range7 Data Retention Characteristics Over the Operating Range8 Thermal Resistance8AC Test Loads and Waveforms Data Retention Waveform45 ns Parameter Description Unit Min Max Read Cycle Write CycleSwitching Waveforms 14 Read Cycle 1 Address Transition Controlled14Read Cycle No OE Controlled15 Write Cycle No WE Controlled13, 17 Write Cycle No CE Controlled13, 17Data I/O Write Cycle No WE Controlled, OE LOW18 Write Cycle No BHE/BLE Controlled, OE LOW18DATAI/O Data Inputs/Outputs Mode Power Ordering Code Package Package Type Operating Diagram RangeOrdering Information BHE BLEPackage Diagrams Pin Vfbga 6 x 8 x 1 mmPin Tsop II Issue Date Orig. Description of Change Document HistoryREV ECN no