Cypress CY62136EV30 manual Write Cycle No WE Controlled13, 17, Write Cycle No CE Controlled13, 17

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CY62136EV30

MoBL®

Switching Waveforms (continued)[14, 15]

Write Cycle No. 1 (WE Controlled)[13, 17, 18]

 

tWC

 

ADDRESS

 

 

CE

tSCE

 

 

 

tAW

 

tHA

tSA

tPWE

 

WE

 

 

BHE/BLE

tBW

 

OE

 

 

 

tSD

t

 

 

HD

DATA I/O

 

 

 

 

 

 

 

 

 

 

 

DATAIN

 

NOTE 19

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tHZOE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle No. 2 (CE Controlled)[13, 17, 18]

 

 

tWC

 

ADDRESS

 

 

 

 

 

tSCE

 

CE

 

 

 

 

tSA

 

tHA

 

tAW

 

WE

 

tPWE

 

 

 

 

BHE/BLE

 

tBW

 

OE

 

 

 

 

 

tSD

t

 

 

 

HD

DATA I/O

NOTE 19

DATAIN

 

 

tHZOE

 

 

Notes:

17.Data I/O is high impedance if OE = VIH.

18.If CE goes HIGH simultaneously with WE = VIH, the output remains in a high-impedance state.

19.During this period, the I/Os are in output state and input signals should not be applied.

Document #: 38-05569 Rev. *B

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Contents Logic Block Diagram FeaturesCypress Semiconductor Corporation Max Pin Configuration2Product Portfolio4 Vfbga Top View Tsop II Top ViewMaximum Ratings Electrical Characteristics Over the Operating Range 5, 6Operating Range7 Data Retention Waveform Data Retention Characteristics Over the Operating Range8Thermal Resistance8 AC Test Loads and WaveformsWrite Cycle 45 ns Parameter Description Unit Min Max Read CycleRead Cycle 1 Address Transition Controlled14 Switching Waveforms 14Read Cycle No OE Controlled15 Write Cycle No CE Controlled13, 17 Write Cycle No WE Controlled13, 17Data I/O Write Cycle No BHE/BLE Controlled, OE LOW18 Write Cycle No WE Controlled, OE LOW18DATAI/O Data BHE BLE Inputs/Outputs Mode PowerOrdering Code Package Package Type Operating Diagram Range Ordering InformationPin Vfbga 6 x 8 x 1 mm Package DiagramsPin Tsop II Document History Issue Date Orig. Description of ChangeREV ECN no