Cypress CY62137FV30 manual Features, Functional Description, Logic Block Diagram

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CY62137FV30 MoBL®

2-Mbit (128K x 16) Static RAM

Features

■Very high speed: 45 ns

■Temperature ranges

❐Industrial: –40°C to +85°C

❐Automotive-A: –40°C to +85°C

❐Automotive-E: –40°C to +125°C

■Wide voltage range: 2.20V–3.60V

■Pin compatible with CY62137CV/CV25/CV30/CV33, CY62137V, and CY62137EV30

■Ultra low standby power

❐Typical standby current: 1 μA

❐Maximum standby current: 5 μA (Industrial)

■Ultra low active power

❐Typical active current: 1.6 mA at f = 1 MHz (45 ns speed)

■Easy memory expansion with CE and OE features

■Automatic power down when deselected

■CMOS for optimum speed and power

■Byte power down feature

■Available in Pb free 48-Ball VFBGA and 44-pin TSOP II package

Functional Description

The CY62137FV30 is a high performance CMOS static RAM organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption by 90% when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The input and output pins (IO0 through IO15) are placed in a high impedance state in the following conditions:

■Deselected (CE HIGH)

■Outputs are disabled (OE HIGH

■Both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH)

■Write operation is active (CE LOW and WE LOW)

Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7) is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A16).

Read from the device by taking Chip Enable (CE) and Output Enable (OE) LOW, while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the “Truth Table” on page 9 for a complete description of read and write modes.

For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.

Logic Block Diagram

DATA IN DRIVERS

A10

 

 

 

 

 

A9

 

 

 

 

DECODER

 

 

A8

 

 

 

 

 

 

A7

 

 

 

 

 

 

 

 

 

 

 

 

 

A6

 

 

 

 

 

 

 

 

 

 

A5

 

 

 

 

 

 

 

 

 

 

A4

 

 

 

 

ROW

 

 

A3

 

 

 

 

 

 

 

 

 

 

 

 

 

A2

 

 

 

 

 

 

 

 

A1

 

 

 

 

 

 

 

 

A0

 

 

 

 

 

 

 

 

128K x 16 RAM Array

SENSE AMPS

IO0–IO7

IO8–IO15

POWER DOWN

CIRCUIT

CE

BHE

BLE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

COLUMN DECODER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BHE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OE

11

12

13

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15

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A

A A

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A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cypress Semiconductor Corporation • 198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Document Number: 001-07141 Rev. *F

 

Revised January 2, 2008

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Contents Logic Block Diagram FeaturesFunctional Description Cypress Semiconductor Corporation 198 Champion CourtProduct Portfolio Pin ConfigurationMin Max TypMaximum Ratings Electrical CharacteristicsCapacitance Device Range AmbientThermal Resistance Data Retention CharacteristicsAC Test Loads and Waveforms Data Retention WaveformSwitching Characteristics Address Switching WaveformsData OUT Previous Data Valid Write Cycle 2 CE Controlled 16, 20 Write Cycle 1 WE Controlled 16, 20Write Cycle 3 WE Controlled, OE LOW Truth Table Inputs or Outputs Mode PowerBHE BLE CY62137FV30LL-45BVI 51-85150 Ball Vfbga Package DiagramPin Tsop Document History Issue Orig. Date Change Description of ChangeREV ECN no

CY62137FV30 specifications

The Cypress CY62137FV30 is a high-performance SRAM (Static Random Access Memory) device designed for high-speed applications. It features a 4-Mbit memory capacity organized into a 512K x 8-bit configuration, making it suitable for a wide range of embedded systems, computing, and communication applications.

One of the standout features of the CY62137FV30 is its fast access time, with speeds as low as 30 ns. This rapid response capability is essential for applications requiring fast data retrieval, such as telecommunications equipment, automotive systems, and consumer electronics where performance is critical. The device also supports a wide operating voltage range from 2.7V to 3.6V, providing flexibility for use in various power-sensitive applications.

In terms of packaging, the CY62137FV30 is available in compact form factors, allowing for designs with space constraints. It comes in standard packages such as TSOPII and SOJ, which are well-regarded in the industry for ease of integration into circuit boards.

The CY62137FV30 employs advanced CMOS technology, ensuring low power consumption while maintaining high-speed performance. This is particularly beneficial in battery-operated devices where power efficiency is a priority. The device offers both read and write cycles, allowing for seamless data operations. Additionally, the SRAM architecture supports asynchronous operations, allowing users to access memory without the need for a clock signal.

The memory is designed with built-in write protection features, enhancing data integrity during critical operations. It is compatible with various standard memory interfaces, making it easy to integrate into different system architectures. Moreover, the device can endure a significant number of read and write cycles, ensuring durability and reliability over extended use.

The CY62137FV30 also features a simple interface, with easy-to-use control signals, which facilitate straightforward integration and design flexibility. Its ability to handle dynamic data and provide quick access to stored information makes it an excellent choice for applications like networking equipment, industrial automation, and high-performance computing systems.

In summary, the Cypress CY62137FV30 is a versatile SRAM solution that combines high speed, low power consumption, and compact packaging. Its innovative technology and reliable performance make it an excellent choice for various applications requiring efficient and fast memory solutions.
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