Cypress CY62137FV30 manual Switching Characteristics

CY62137FV30 MoBL®

Switching Characteristics

Over the Operating Range [11, 12]

Parameter			Description	45 ns (Ind’l/Auto-A)		55 ns (Auto-E)		Unit
				Min	Max	Min	Max
Read Cycle
tRC	Read Cycle Time			45		55		ns
tAA	Address to Data Valid				45		55	ns
tOHA	Data Hold From Address Change			10		10		ns
tACE		LOW to Data Valid			45		55	ns
	CE
tDOE		LOW to Data Valid			22		25	ns
	OE
tLZOE		LOW to Low Z [13]		5		5		ns
	OE
tHZOE		HIGH to High Z [13, 14]			18		20	ns
	OE
tLZCE		LOW to Low Z [13]		10		10		ns
	CE
tHZCE		HIGH to High Z [13, 14]			18		20	ns
	CE
tPU		LOW to Power Up		0		0		ns
	CE
tPD		HIGH to Power Down			45		55	ns
	CE
tDBE					45		55	ns
	BLE/BHE LOW to Data Valid
tLZBE				5		10		ns
	BLE/BHE LOW to Low Z [13, 15]
tHZBE					18		20	ns
	BLE/BHE HIGH to High Z [13, 14]
Write Cycle [16]
tWC	Write Cycle Time			45		55		ns
tSCE		LOW to Write End		35		40		ns
	CE
tAW	Address Setup to Write End			35		40		ns
tHA	Address Hold from Write End			0		0		ns
tSA	Address Setup to Write Start			0		0		ns
tPWE		Pulse Width		35		40		ns
	WE
tBW				35		40		ns
	BLE/BHE LOW to Write End
tSD	Data Setup to Write End			25		25		ns
tHD	Data Hold From Write End			0		0		ns
tHZWE		LOW to High Z [13, 14]			18		20	ns
	WE
tLZWE		HIGH to Low Z [13]		10		10		ns
	WE

Notes

11.Test conditions for all parameters, other than tri-state parameters, assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in “AC Test Loads and Waveforms” on page 4.

12.AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see application note AN13842 for further clarification.

13.At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.

14.tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.

15.If both byte enables are toggled together, this value is 10 ns.

16.The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals are ACTIVE to initiate a write and any of these signals terminate a write by going INACTIVE. The data input setup and hold timing are referenced to the edge of the signal that terminates the write.

Document Number: 001-07141 Rev. *F Page 5 of 12

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