Cypress STK12C68-5 manual Sram Write Cycle 1 WE Controlled 11, Sram Write Cycle 2 CE Controlled 11

STK12C68-5 (SMD5962-94599)

SRAM Write Cycle

	Parameter		Description		35 ns			55 ns		Unit
Cypress		Alt		Min		Max	Min		Max
Parameter
tWC		tAVAV	Write Cycle Time	35			55			ns
tPWE		tWLWH, tWLEH	Write Pulse Width	25			45			ns
tSCE		tELWH, tELEH	Chip Enable To End of Write	25			45			ns
tSD		tDVWH, tDVEH	Data Setup to End of Write	12			25			ns
tHD		tWHDX, tEHDX	Data Hold After End of Write	0			0			ns
tAW		tAVWH, tAVEH	Address Setup to End of Write	25			45			ns
tSA		tAVWL, tAVEL	Address Setup to Start of Write	0			0			ns
tHA	[9,10]	tWHAX, tEHAX	Address Hold After End of Write	0			0			ns
tHZWE		tWLQZ	Write Enable to Output Disable			13			15	ns
tLZWE	[9]	tWHQX	Output Active After End of Write	5			5			ns

Switching Waveforms

Figure 10. SRAM Write Cycle 1: WE Controlled [11, 12]

	tWC
ADDRESS
	tSCE
CE
	tAW
	tSA
WE	tPWE
	tSD
DATA IN	DATA VALID
	tHZWE
	HIGH IMPEDANCE

DATA OUT PREVIOUS DATA

tHA

tHD

tLZWE

Figure 11. SRAM Write Cycle 2: CE Controlled [11, 12]

ADDRESS

CE

WE

DATA IN

DATA OUT

tWC

tSA tSCE tHA

tAW

tPWE

tSD tHD

DATA VALID

HIGH IMPEDANCE

Notes

10.If WE is Low when CE goes Low, the outputs remain in the high impedance state.

11.HSB must be high during SRAM Write cycles.

12.CE or WE must be greater than VIH during address transitions.

Document Number: 001-51026 Rev. ** Page 10 of 18

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