AutoStore Inhibit Mode, Software Store | Cypress STK12C68-5 guide

Figure 4. AutoStore Inhibit Mode
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9&$3	9FF
	+6%

9VV

If the power supply drops faster than 20 us/volt before Vcc reaches VSWITCH, then a 2.2 ohm resistor must be connected between VCC and the system supply to avoid momentary excess of current between VCC and VCAP.

AutoStore Inhibit Mode

If an automatic STORE on power loss is not required, then VCC is tied to ground and +5V is applied to VCAP (Figure 4). This is the AutoStore Inhibit mode, where the AutoStore function is disabled. If the STK12C68-5 is operated in this configuration, references to VCC are changed to VCAP throughout this data sheet. In this mode, STORE operations are triggered through software control or the HSB pin. To enable or disable Autostore using an IO port pin see Preventing Store on page 5. It is not permissible to change between these three options “on the fly”.

Hardware STORE (HSB) Operation

The STK12C68-5 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin is used to request a hardware STORE cycle. When the HSB pin is driven LOW, the STK12C68-5 conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a Write to the SRAM takes place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition, while the STORE (initiated by any means) is in progress.

SRAM Read and Write operations, that are in progress when HSB is driven LOW by any means, are given time to complete before the STORE operation is initiated. After HSB goes LOW, the STK12C68-5 continues SRAM operations for tDELAY. During tDELAY, multiple SRAM Read operations take place. If a Write is in progress when HSB is pulled LOW, it allows a time, tDELAY to complete. However, any SRAM Write cycles requested after HSB goes LOW are inhibited until HSB returns HIGH.

Document Number: 001-51026 Rev. **

STK12C68-5 (SMD5962-94599)

During any STORE operation, regardless of how it is initiated, the STK12C68-5 continues to drive the HSB pin LOW, releasing it only when the STORE is complete. After completing the STORE operation, the STK12C68-5 remains disabled until the HSB pin returns HIGH.

If HSB is not used, it is left unconnected.

Hardware RECALL (Power Up)

During power up or after any low power condition (VCC < VRESET), an internal RECALL request is latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete.

If the STK12C68-5 is in a Write state at the end of power up RECALL, the SRAM data is corrupted. To help avoid this situation, a 10 Kohm resistor is connected either between WE and system VCC or between CE and system VCC.

Software STORE

Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK12C68-5 software STORE cycle is initiated by executing sequential CE controlled Read cycles from six specific address locations in exact order. During the STORE cycle, an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements. When a STORE cycle is initiated, input and output are disabled until the cycle is completed.

Because a sequence of Reads from specific addresses is used for STORE initiation, it is important that no other Read or Write accesses intervene in the sequence. If they intervene, the sequence is aborted and no STORE or RECALL takes place.

To initiate the software STORE cycle, the following Read sequence is performed:

1.Read address 0x0000, Valid READ

2.Read address 0x1555, Valid READ

3.Read address 0x0AAA, Valid READ

4.Read address 0x1FFF, Valid READ

5.Read address 0x10F0, Valid READ

6.Read address 0x0F0F, Initiate STORE cycle

The software sequence is clocked with CE controlled Reads or OE controlled Reads. When the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. It is important that Read cycles and not Write cycles are used in the sequence. It is not necessary that OE is LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is again activated for Read and Write operation.

Software RECALL

Data is transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of Read operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled Read operations is performed: