Cypress STK12C68-5 manual Hardware Store Cycle

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STK12C68-5 (SMD5962-94599)

Hardware STORE Cycle

	Parameter	Alt	Description	STK12C68-5		Unit
	Parameter	Alt	Description	Min	Max	Unit
				Min	Max
t	[9, 14]	tHLHZ	STORE Cycle Duration		10	ms
	STORE
t	[14, 19]	tRECOVER, tHHQX	Hardware STORE High to Inhibit Off		700	ns
	DHSB
tPHSB		tHLHX	Hardware STORE Pulse Width	15		ns
tHLBL			Hardware STORE Low to STORE Busy		300	ns

Note

19. tDHSB is only applicable after tSTORE is complete.

Document Number: 001-51026 Rev. **

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Contents Logic Block Diagram FeaturesFunctional Description Cypress Semiconductor Corporation 198 Champion CourtPin Definitions PinoutsSram Read Device OperationSram Write AutoStore OperationHardware Recall Power Up AutoStore Inhibit ModeHardware Store HSB Operation Software StoreData Protection Low Average Active PowerNoise Considerations Hardware ProtectA12-A0 Mode Power Hardware Mode SelectionBest Practices Range Ambient Temperature DC Electrical CharacteristicsMaximum Ratings Operating RangeCapacitance Data Retention and EnduranceThermal Resistance AC Test ConditionsSwitching Waveforms AC Switching CharacteristicsParameter Description 35 ns 55 ns Unit Cypress Alt Min Max ParameterSram Write Cycle 2 CE Controlled 11 Sram Write Cycle 1 WE Controlled 11Switching Waveform AutoStore or Power Up RecallParameter Alt Description STK12C68-5 Unit Min Max Parameter Alt Description 35 ns 55 ns Unit Min Max Software Controlled STORE/RECALL CycleHardware Store Cycle Hardware Store CycleSMD5962 94599 01 MX Part Numbering Nomenclature STK12C68 5 C 35 MPin LCC 350 mil Ordering InformationPin 300-Mil Side Braze DIL Package DiagramsPad 350-Mil LCC New data sheet Sales, Solutions, and Legal InformationDocument History