Cypress CY62128E Maximum Ratings, Electrical Characteristics Over the Operating Range, Gnd Vi Vcc

MoBL® CY62128E

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.

Storage Temperature –65°C to +150°C

Output Current into Outputs (LOW)	............................. 20 mA
Static Discharge Voltage	> 2001V
(MIL-STD-883, Method 3015)
Latch up Current	> 200 mA

Ambient Temperature with
Power Applied	–55°C to +125°C
Supply Voltage to Ground
Potential	–0.5V to 6.0V (VCC(max) + 0.5V)
DC Voltage Applied to Outputs
in High-Z State[5, 6]	–0.5V to 6.0V (V	CC(max)	+ 0.5V)
DC Input Voltage[5, 6]
	–0.5V to 6.0V (V	CC(max)	+ 0.5V)

Electrical Characteristics (Over the Operating Range)

Operating Range

Device	Range	Ambient	[7]
		Temperature	VCC
CY62128ELL	Ind’l/Auto-A	–40°C to +85°C	4.5V to 5.5V
	Auto-E	–40°C to +125°C

Parameter

Description

Test Conditions

45 ns (Ind’l/Auto-A)

55 ns (Auto-E)

Unit

Min

Typ[3]

Max

Min

Typ[3]

Max

VOH

Output HIGH

IOH = –1 mA

2.4

2.4

V

Voltage

VOL

Output LOW

IOL = 2.1 mA

0.4

0.4

V

Voltage

VIH

Input HIGH Voltage

VCC = 4.5V to 5.5V

2.2

VCC + 0.5

2.2

VCC + 0.5

V

VIL

Input LOW voltage

VCC = 4.5V to 5.5V

–0.5

0.8

–0.5

0.8

V

IIX

Input Leakage

GND < VI < VCC

–1

+1

–4

+4

μA

Current

IOZ

Output Leakage

GND < VO < VCC, Output Disabled

–1

+1

–4

+4

μA

Current

ICC

VCC Operating

f = fmax = 1/tRC

VCC = VCC(max)

11

16

11

35

mA

Supply Current

IOUT = 0 mA

f = 1 MHz

1.3

2

1.3

4

CMOS levels

ISB2 [8]

Automatic CE

1 > VCC – 0.2V or CE2 < 0.2V,

1

4

1

30

μA

CE

Power down

VIN > VCC – 0.2V or VIN < 0.2V,

Current—CMOS

f = 0, VCC = VCC(max)

Inputs

Capacitance (For all Packages) [9]

Parameter	Description	Test Conditions	Max	Unit
CIN	Input Capacitance	TA = 25°C, f = 1 MHz,	10	pF
		VCC = VCC(typ)
COUT	Output Capacitance		10	pF

Notes

5.VIL(min) = –2.0V for pulse durations less than 20 ns.

6.VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.

7.Full device AC operation assumes a 100 μs ramp time from 0 to VCC(min) and 200 μs wait time after VCC stabilization.

8.Only chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.

9.Tested initially and after any design or process changes that may affect these parameters.

Document #: 38-05485 Rev. *F Page 3 of 12

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