Cypress CY62128E manual Write Cycle No CE1 or CE2 Controlled 11, 15, 19, Inputs/Outputs Mode Power

Page 7

MoBL® CY62128E

Switching Waveforms (continued)

Figure 4. Write Cycle No. 2 (CE1 or CE2 Controlled) [11, 15, 19, 20]

 

tWC

 

ADDRESS

 

 

CE

tSCE

 

 

 

 

tSA

 

 

tAW

tHA

 

tPWE

 

WE

 

 

 

tSD

tHD

DATA IO

DATA VALID

 

 

 

Figure 5. Write Cycle No. 3 (WE Controlled, OE LOW) [11, 20]

 

 

tWC

 

ADDRESS

 

 

 

 

 

tSCE

 

CE

 

 

 

 

tAW

 

tHA

 

tSA

tPWE

 

WE

 

 

 

 

 

tSD

tHD

DATA IO

NOTE 21

DATA VALID

 

 

tHZWE

 

tLZWE

Truth Table

CE1

CE2

WE

OE

Inputs/Outputs

Mode

Power

H

X

X

X

High-Z

Deselect/Power down

Standby (ISB)

X

L

X

X

High-Z

Deselect/Power down

Standby (ISB)

L

H

H

L

Data Out

Read

Active (ICC)

L

H

L

X

Data In

Write

Active (ICC)

L

H

H

H

High-Z

Selected, Outputs Disabled

Active (ICC)

Document #: 38-05485 Rev. *F

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesLogic Block Diagram Functional DescriptionInd’l/Auto-A Pin Configuration2Product Portfolio Pin Soic Top ViewGND VI VCC Electrical Characteristics Over the Operating RangeMaximum Ratings Device Range AmbientData Retention Waveform11 Data Retention Characteristics Over the Operating RangeThermal Resistance9 AC Test Loads and WaveformWrite Cycle15 Switching Characteristics Over the Operating Range12Parameter Description Ns Ind’l/Auto-A Ns Auto-E Unit Min Read CycleSwitching Waveforms Write Cycle No CE1 or CE2 Controlled 11, 15, 19 Inputs/Outputs Mode PowerCY62128ELL-55ZAXE Package DiagramsOrdering Information CY62128ELL-45ZAXIPin Shrunk Thin Small Outline Package 8 x 13.4 mm Pin Thin Small Outline Package Type I 8 x 20 mm Submission Orig. Description of Change Date Document HistoryUSB Sales, Solutions, and Legal Information