Cypress CY62128E Pin Configuration2, Product Portfolio, Pin Soic Top View, Ind’l/Auto-A, Auto-E

Page 2

MoBL® CY62128E

Pin Configuration[2]

32-Pin SOIC Top View

A11

 

1

 

A9

 

2

 

A8

 

3

 

A13

 

4

 

WE

 

5

CE2

 

6

 

A15

 

7

 

VCC

 

8

 

 

 

32

 

 

OE

 

 

31

 

 

A10

 

 

 

 

30

 

 

CE1

 

29

 

 

IO7

 

 

 

 

28

 

 

IO6

 

 

 

TSOP I

27

 

 

IO5

26

 

 

IO4

 

 

Top View

25

 

 

IO3

 

 

(not to scale)

 

 

 

 

 

NC

A16 A14 A12

A7 A6 A5 A4 A3 A2 A1 A0 IO0 IO1 IO2

VSS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

VCC

A15

CE2

WE

A13

A8

A9

A11

OE

A10

CE1

IO7

IO6

IO5

IO4

IO3

NC

 

9

A16

 

10

A14

 

11

A12

 

12

A7

 

13

 

A6

 

14

A5

 

15

 

A4

 

16

 

 

 

 

 

 

A11

 

 

25

 

 

A9

 

 

26

 

 

A8

 

 

276

A13

 

 

28

WE

 

 

29

CE2

 

 

30

 

 

A15

 

 

31

VCC

 

 

32

 

 

NC

 

 

1

A16

 

 

2

 

 

A14

 

 

3

A12

 

 

4

A7

 

 

5

 

 

A6

 

 

6

A5

 

 

7

 

 

A4

 

 

8

 

 

 

24

 

 

 

GND

 

23

 

 

 

IO2

 

 

 

 

 

22

 

 

 

IO1

 

21

 

 

 

IO0

 

 

 

 

 

20

 

 

 

A0

 

19

 

 

 

A1

 

18

 

 

 

A2

 

17

 

 

 

A3

 

 

 

 

 

24

 

 

 

 

 

 

 

 

 

 

 

OE

 

 

23

 

 

 

 

A10

 

 

 

 

 

22

 

 

 

 

CE1

 

21

 

 

 

 

IO7

 

 

 

 

 

20

 

 

 

 

IO6

 

 

 

 

STSOP

19

 

 

 

 

IO5

18

 

 

 

 

IO4

 

 

 

Top View

17

 

 

 

 

IO3

(not to scale)

16

 

 

 

 

GND

 

 

 

 

15

 

 

 

 

IO2

 

 

 

 

 

14

 

 

 

 

IO1

 

13

 

 

 

 

IO0

 

12

 

 

 

 

A0

 

 

 

 

 

11

 

 

 

 

A1

 

10

 

 

 

 

A2

 

9

 

 

 

 

A3

 

 

 

 

Product Portfolio

 

 

 

 

 

 

 

 

 

 

Power Dissipation

 

Product

Range

 

VCC Range (V)

Speed

 

Operating ICC (mA)

 

 

 

(ns)

 

Standby ISB2 (µA)

 

 

 

 

 

 

 

f = 1MHz

f = fmax

 

 

 

 

 

 

 

 

 

 

 

Min

 

Typ[3]

Max

 

Typ[3]

 

Max

Typ[3]

Max

Typ[3]

Max

CY62128ELL

Ind’l/Auto-A

4.5

 

5.0

5.5

45 [4]

1.3

 

2

11

16

1

4

CY62128ELL

Auto-E

4.5

 

5.0

5.5

55

1.3

 

4

11

35

1

30

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes

2.NC pins are not connected on the die.

3.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.

4.When used with a 100 pF capacitive load and resistive loads as shown on page 4, access times of 55 ns (tAA, tACE) and 25 ns (tDOE) are guaranteed.

Document #: 38-05485 Rev. *F

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Contents Functional Description FeaturesLogic Block Diagram Cypress Semiconductor Corporation 198 Champion CourtPin Soic Top View Pin Configuration2Product Portfolio Ind’l/Auto-ADevice Range Ambient Electrical Characteristics Over the Operating RangeMaximum Ratings GND VI VCCAC Test Loads and Waveform Data Retention Characteristics Over the Operating RangeThermal Resistance9 Data Retention Waveform11Read Cycle Switching Characteristics Over the Operating Range12Parameter Description Ns Ind’l/Auto-A Ns Auto-E Unit Min Write Cycle15Switching Waveforms Inputs/Outputs Mode Power Write Cycle No CE1 or CE2 Controlled 11, 15, 19CY62128ELL-45ZAXI Package DiagramsOrdering Information CY62128ELL-55ZAXEPin Shrunk Thin Small Outline Package 8 x 13.4 mm Pin Thin Small Outline Package Type I 8 x 20 mm Document History Submission Orig. Description of Change DateSales, Solutions, and Legal Information USB