Cypress CY62128E manual Document History, Submission Orig. Description of Change Date

Page 11

MoBL® CY62128E

Document History Page

Document Title: CY62128E MoBL® 1-Mbit (128K x 8) Static RAM

Document Number: 38-05485

Revision

ECN

Submission

Orig. of

Description of Change

Date

Change

 

 

 

 

 

 

 

 

**

203120

See ECN

AJU

New data sheet

 

 

 

 

 

*A

299472

See ECN

SYT

Converted from Advance Information to Preliminary

 

 

 

 

Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns, respectively

 

 

 

 

Changed tDOE from 15 ns to 18 ns for 35 ns speed bin

 

 

 

 

Changed tHZOE, tHZWE from 12 and 15 ns to 15 and 18 ns for the 35 and 45 ns

 

 

 

 

speed bins, respectively

 

 

 

 

Changed tHZCE from 12 and 15 ns to 18 and 22 ns for the 35 and 45 ns speed

 

 

 

 

bins, respectively

 

 

 

 

Changed tSCE from 25 and 40 ns to 30 and 35 ns for the 35 and 45 ns speed

 

 

 

 

bins, respectively

 

 

 

 

Changed tSD from 15 and 20 ns to 18 and 22 ns for the 35 and 45 ns speed bins,

 

 

 

 

respectively

 

 

 

 

Added Pb-free package information

 

 

 

 

Added footnote #9

 

 

 

 

Changed operating range for SOIC package from Commercial to Industrial

 

 

 

 

Modified signal transition time from 5 ns to 3 ns in footnote #11

 

 

 

 

Changed max of ISB1, ISB2 and ICCDR from 1.0 μA to 1.5 μA

*B

461631

See ECN

NXR

Converted from Preliminary to Final

 

 

 

 

Included Automotive Range and 55 ns speed bin

 

 

 

 

Removed 35 ns speed bin

 

 

 

 

Removed “L” version of CY62128E

 

 

 

 

Removed Reverse TSOP I package from Product offering

 

 

 

 

Changed ICC (Typ) from 8 mA to 11 mA and ICC (max) from 12 mA to 16 mA for f

 

 

 

 

= fmax

 

 

 

 

Changed ICC (max) from 1.5 mA to 2.0 mA for f = 1 MHz

 

 

 

 

Removed ISB1 DC Specs from Electrical characteristics table

 

 

 

 

Changed ISB2 (max) from 1.5 μA to 4 μA

 

 

 

 

Changed ISB2 (Typ) from 0.5 μA to 1 μA

 

 

 

 

Changed ICCDR (max) from 1.5 μA to 4 μA

 

 

 

 

Changed the AC Test load Capacitance value from 100 pF to 30 pF

 

 

 

 

Changed tLZOE from 3 to 5 ns

 

 

 

 

Changed tLZCE from 6 to 10 ns

 

 

 

 

Changed tHZCE from 22 to 18 ns

 

 

 

 

Changed tPWE from 30 to 35 ns

 

 

 

 

Changed tSD from 22 to 25 ns

 

 

 

 

Changed tLZWE from 6 to 10 ns

 

 

 

 

Updated the Ordering Information Table

*C

464721

See ECN

NXR

Updated the Block Diagram on page # 1

 

 

 

 

 

*D

563144

See ECN

AJU

Added footnote 4 on page 2

 

 

 

 

 

*E

1024520

See ECN

VKN

Added Automotive-A information

 

 

 

 

Converted Automotive-E specs to final

 

 

 

 

Added footnote #9 related to ISB2 and ICCDR

 

 

 

 

Updated Ordering Information table

*F

2548575

08/05/08

NXR

Corrected typo error in Ordering Information table

 

 

 

 

 

Document #: 38-05485 Rev. *F

Page 11 of 12

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesLogic Block Diagram Functional DescriptionInd’l/Auto-A Pin Configuration2Product Portfolio Pin Soic Top ViewGND VI VCC Electrical Characteristics Over the Operating RangeMaximum Ratings Device Range AmbientData Retention Waveform11 Data Retention Characteristics Over the Operating RangeThermal Resistance9 AC Test Loads and WaveformWrite Cycle15 Switching Characteristics Over the Operating Range12Parameter Description Ns Ind’l/Auto-A Ns Auto-E Unit Min Read CycleSwitching Waveforms Write Cycle No CE1 or CE2 Controlled 11, 15, 19 Inputs/Outputs Mode PowerCY62128ELL-55ZAXE Package DiagramsOrdering Information CY62128ELL-45ZAXIPin Shrunk Thin Small Outline Package 8 x 13.4 mm Pin Thin Small Outline Package Type I 8 x 20 mm Submission Orig. Description of Change Date Document HistoryUSB Sales, Solutions, and Legal Information