STK17T88
minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles.
If a binary “1” is loaded into the register, only the first 2 minutes of the 64 minute cycle is modified; if a binary 6 is loaded, the first 12 are affected, and so on. Therefore each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles. That is +4.068 or
The calibration register value is determined during system test by setting the CAL bit in the Flags register (at 0x7FF0) to 1. This causes the INT pin to toggle at a nominal 512 Hz. This frequency can be measured with a frequency counter. Any deviation measured from the 512 Hz indicates the degree and direction of the required correction. For example, a reading of 512.01024 Hz would indicate a +20 ppm error, requiring a
To set or clear CAL, set the write bit “W” (in the Flags register at 0x7FF0) to a “1” to enable writes to the Flags register. Write a value to CAL and then reset the write bit to “0” to disable writes.
The default Calibration register value from the factory is 00h. The user calibration value loaded is retained during a power loss.
Alarm
The alarm function compares a
Each of the alarm registers has a match bit as its MSB. Setting the match bit to a 1 disables this alarm register from the alarm comparison. When the match bit is 0, the alarm register is compared with the equivalent real time clock register. Using the match bits, an alarm can occur as specifically as one particular second on one day of the month or as frequently as once per minute.
Note The product requires the match bit for seconds (0x7FF2, bit D7) be set to 0 for proper operation of the Alarm Flag and Interrupt.
The alarm value should be initialized on power up by software since the alarm registers are not nonvolatile.
To set or clear the Alarm registers, set the write bit “W” (in the Flags register at 0x7FF0) to a “1” to enable writes to the Alarm registers. Write an alarmvalue to the alarm registers and then reset the write bit to “0” to disable writes.
Watchdog Timer
The watchdog timer is designed to interrupt or reset the processor should its program get hung in a loop and not respond in a timely manner. The software must reload the watchdog timer before it counts down to zero to prevent this interrupt or reset.
The watchdog timer is a
The watchdog counter is loaded with a starting value from the load register and then counts down to zero, setting the watchdog flag (WDF) and generating an interrupt if the watchdog interrupt is enabled. The watchdog flag bit is reset when the Flags register is read. The operating software would normally reload the counter by setting the watchdog strobe bit (WDS) to 1 within the timing interval programmed into the load register.
To use the watchdog timer to reset the processor on timeout, the INT is tied to processor master reset and Interrupt register is programmed to 24h to enable interrupts to pulse the reset pin on timeout.
To load the watchdog timer, set a new value into the load register by writing a “0” to the watchdog write bit (WDW) of the watchdog register (at 0x7FF7). Then load a new value into the load register. Once the new value is loaded, the watchdog write bit is then set to 1 to disable watchdog writes. The watchdog strobe bit (WDS) is set to 1 to load this value into the watchdog timer. Note: Setting the load register to zero disables the watchdog timer function.
The system software should initialize the watchdog load register on power up to the desired value since the register is not nonvol- atile.
Power Monitor
The STK17T88 provides a power monitor function. The power monitor is based on an internal
When the power supply drops below VSWITCH, the real time clock circuit is switched to the backup supply (battery or capacitor).
When operating from the backup source, no data may be read or written and the clock functions are not available to the user. The clock continues to operate in the background. Updated clock data is available to the user tHRECALL delay after VCC has been restored to the device.
When the power is lost, the PF flag in the Flags register is set to indicate the power failure and an interrupt is generated if the power fail interrupt is enabled (interrupt register=20h). The INT line would normally be tied to the processor master reset input to perform
Interrupts
The STK17T88 has a Flags register, Interrupt register, and interrupt logic that can interrupt the microcontroller or general a power up master reset signal. There are three potential interrupt sources: the watchdog timer, the power monitor, and the clock alarm. Each can be individually enabled to drive the INT pin by setting the appropriate bit in the Interrupt register. In addition, each has an associated flag bit in the Flags register that the host processor can read to determine the interrupt source. Two bits in the interrupt register determine the operation of the INT pin driver.
Document Number: | Page 15 of 22 |
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