Cypress STK17T88 manual Features, Description, Logic Block Diagram

Page 1

STK17T88

32K x 8 AutoStore™ nvSRAM with Real Time Clock

Features

nvSRAM Combined With Integrated Real-Time Clock Functions (RTC, Watchdog Timer, Clock Alarm, Power Monitor)

Capacitor or Battery Backup for RTC

25, 45 ns Read Access and R/W Cycle Time

Unlimited Read/Write Endurance

Automatic Nonvolatile STORE on Power Loss

Nonvolatile STORE Under Hardware or Software Control

Automatic RECALL to SRAM on Power Up

Unlimited RECALL Cycles

200K STORE Cycles

20-Year Nonvolatile Data Retention

Single 3V +20%, -10% Power Supply

Commercial and Industrial Temperatures

48-pin 300-mil SSOP Package (RoHS-Compliant)

Description

The Cypress STK17T88 combines a 256 Kb nonvolatile static RAM (nvSRAM) with a full-featured real-time clock in a reliable, monolithic integrated circuit.

The 256 Kb nvSRAM is a fast static RAM with a nonvolatile Quantum Trap storage element included with each memory cell.

The SRAM provides the fast access and cycle times, ease of use and unlimited read and write endurance of a normal SRAM. Data transfers automatically to the nonvolatile storage cells when power loss is detected (the STORE operation). On power up, data is automatically restored to the SRAM (the RECALL operation). Both STORE and RECALL operations are also available under software control.

The real time clock function provides an accurate clock with leap year tracking and a programmable, high accuracy oscillator. The Alarm function is programmable for one-time alarms or periodic minutes, hours, or days alarms. There is also a programmable watchdog timer for processor control.

Logic Block Diagram

 

 

 

 

 

 

 

 

 

 

 

 

Quantum Trap

VCC

VCAP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

512 X 512

POWER

VRTCbat

 

 

A5

 

 

 

 

 

 

DECODER

 

 

 

CONTROL

VRTCcap

 

 

A6

 

 

STORE

 

 

 

 

 

 

 

 

A7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A8

 

STATIC RAM

RECALL

STORE/

 

 

 

A9

 

ARRAY

RECALL

HSB

 

 

A11

ROW

 

512 X 512

 

CONTROL

 

 

A12

 

 

 

 

 

 

 

 

A13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A14

 

 

 

 

 

SOFTWARE

A13 – A0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DETECT

 

 

DQ0

BUFFERS

 

COLUMN I/O

 

 

 

 

 

 

DQ1

 

 

 

 

 

X1

 

DQ2

 

COLUMN DEC

 

 

RTC

 

 

DQ3

 

 

 

 

 

X2

 

DQ4

 

 

 

 

 

 

INT

 

INPUT

 

 

 

 

 

 

 

DQ5

 

A0 A1 A2 A3 A4 A10

 

 

 

 

 

 

DQ6

 

 

 

 

MUX

 

A14 – A0

 

DQ7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

G

 

 

 

 

 

 

 

 

 

E

 

 

 

 

 

 

 

 

 

W

 

Cypress Semiconductor Corporation

198 Champion Court

San Jose, CA 95134-1709

408-943-2600

Document Number: 001-52040 Rev. *A

 

 

 

 

 

 

Revised March 17, 2009

[+] Feedback

Image 1
Contents Logic Block Diagram FeaturesDescription Cypress Semiconductor CorporationPin Descriptions Pin ConfigurationsRF SSOP-48 Package Thermal Characteristics DC CharacteristicsSymbol Parameter Commercial Industrial Units Min Absolute Maximum RatingsCapacitance AC Test ConditionsIbak RTC DC CharacteristicsSram Read Cycles #1 and #2 Symbols Parameter STK17T88-25 STK17T88-45 Units Alt Min MaxSram Write Cycles #1 and #2 Symbols Parameter STK17T88-25 STK17T88-45 Units Alt MinMin Max Symbols Parameter STK17T88 Units Standard Alternate Min Max AutoStore/Power Up RecallCONTROLLED13 Software-Controlled STORE/RECALL CycleHardware Store to Sram Disabled Soft Sequence CommandsSymbols Parameter STK17T88 Units Standard Min Max Hardware Store CycleA14-A0 Mode Mode SelectionNvSRAM Operation Hardware Recall Power UPAutoStore Operation Hardware Store HSB OperationNoise Considerations Software StorePreventing AutoStore Best PracticesReal Time Clock Watchdog Timer AlarmPower Monitor Flags Register Interrupt RegisterRegister BCD Format Data Function / Range RTC Register MapOscen WDS WDW WDTRegister Map Detail 0x7FF4 Alarm Hours 10s Alarm Hours 0x7FF5 Alarm Day0x7FF3 Alarm Minutes 0x7FF2 Alarm SecondsOrdering Code Description Access Times ns Temperature User must reset this bit to 0 to clear this conditionOrdering Codes 0x7FF0 FlagsPackage Diagram Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationDocument History