Cypress STK17T88 manual Interrupt Register, Flags Register

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STK17T88

Figure 15 is a functional diagram of the interrupt logic.

Figure 15. Interrupt Block Diagram

WDF

Watchdog

Timer WIE

High/Low (H/L). When set to a 1, the INT pin is active high and the driver mode is push-pull. The INT pin can drive high only when VCC>VSWITCH. When set to a 0, the INT pin is active low and the drive mode is open-drain. The active low (open drain) output is maintained even when power is lost.

Pulse/Level (P/L). When set to a 1, the INT pin is driven for

Power Monitor

VINT

PF

PFE

P/L

Pin

Driver

H/L

VCC

INT

VSS

approximately 200 ms when the interrupt occurs. The pulse is reset when the Flags register is read. When P/L is set to a 0, the INT pin is driven high or low (determined by H/L) until the Flags register is read.

AF

Clock

Alarm AIE

The Interrupt register is loaded with the default value 00h at the factory. The user should configure the Interrupt register to the value desired for their desired mode of operation. Once configured, the value is retained during power failures.

Interrupt Register

Watchdog Interrupt Enable (WIE). When set to 1, the watchdog timer drives the INT pin when a watchdog time-out occurs. When WIE is set to 0, the watchdog time-out only sets the WDF flag bit.

Alarm Interrupt Enable (AIE). When set to 1, the INT pin is driven when an alarm match occurs. When set to 0, the alarm match only sets the AF flag bit.

Power Fail Interrupt Enable (PFE). When set to 1, the INT pin is driven by a power fail signal from the power monitor. When set to 0, only the PF flag is set.

Flags Register

The Flags register has three flag bits: WDF, AF, and PF. These flags are set by the watchdog time-out, alarm match, or power fail monitor respectively. The processor can either poll this register or enable the interrupts to be informed when a flag is set. The flags are automatically reset once the register is read.

The Flags register is automatically loaded with the value 00h on power up (with the exception of the OSCF bit).

Document Number: 001-52040 Rev. *A

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Contents Features Logic Block DiagramDescription Cypress Semiconductor CorporationPin Configurations Pin DescriptionsDC Characteristics RF SSOP-48 Package Thermal CharacteristicsSymbol Parameter Commercial Industrial Units Min Absolute Maximum RatingsAC Test Conditions CapacitanceRTC DC Characteristics IbakSymbols Parameter STK17T88-25 STK17T88-45 Units Alt Min Max Sram Read Cycles #1 and #2Sram Write Cycles #1 and #2 Symbols Parameter STK17T88-25 STK17T88-45 Units Alt MinMin Max AutoStore/Power Up Recall Symbols Parameter STK17T88 Units Standard Alternate Min MaxSoftware-Controlled STORE/RECALL Cycle CONTROLLED13Soft Sequence Commands Hardware Store to Sram DisabledSymbols Parameter STK17T88 Units Standard Min Max Hardware Store CycleMode Selection A14-A0 ModeHardware Recall Power UP NvSRAM OperationAutoStore Operation Hardware Store HSB OperationSoftware Store Noise ConsiderationsPreventing AutoStore Best PracticesReal Time Clock Watchdog Timer AlarmPower Monitor Interrupt Register Flags RegisterRTC Register Map Register BCD Format Data Function / RangeOscen WDS WDW WDTRegister Map Detail 0x7FF5 Alarm Day 0x7FF4 Alarm Hours 10s Alarm Hours0x7FF3 Alarm Minutes 0x7FF2 Alarm SecondsUser must reset this bit to 0 to clear this condition Ordering Code Description Access Times ns TemperatureOrdering Codes 0x7FF0 FlagsPackage Diagram Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationDocument History
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