Cypress CY14B101K manual Low Average Active Power Best Practices, Current versus Cycle Time

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CY14B101K

Low Average Active Power

Best Practices

CMOS technology provides the CY14B101K the benefit of drawing significantly less current when it is cycled at times longer than 50 ns. Figure 3 shows the relationship between ICC and READ/WRITE Cycle Time. The worst case current consumption is shown for commercial temperature range, VCC = 3.6V, and chip enable at maximum frequency. Only standby current is drawn when the chip is disabled.

The overall average current drawn by the CY14B101K depends on the following items:

■The duty cycle of chip enable

■The overall cycle rate for accesses

■The ratio of READs to WRITEs

■The operating temperature

■The VCC level

■IO loading

Figure 3. Current versus Cycle Time

nvSRAM products have been used effectively for over 15 years. While ease-of-use is one of the product’s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices:

■The nonvolatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance. Incoming inspection routines at customer or contract manufacturer’s sites sometimes reprograms these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. The end product’s firmware should not assume that an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration and cold or warm boot status, must always program a unique NV pattern (for example, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufac- turing test to ensure these system routines work consistently.

■The OSCEN bit in the Calibration register at 0x1FFF8 should be set to 1 to preserve battery life when the system is in storage (see Stopping and Starting the Oscillator on page 7).

■The Vcap value specified in this data sheet includes a minimum and a maximum value size. The best practice is to meet this requirement and not exceed the maximum Vcap value because the higher inrush currents may reduce the reliability of the internal pass transistor. Customers who want to use a larger Vcap value to make sure there is extra store charge should discuss their Vcap size selection with Cypress.

Document Number: 001-06401 Rev. *I

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Contents Logic Block Diagram FeaturesFunctional Description Cypress Semiconductor Corporation 198 Champion CourtOutput Enable, Active LOW. The active low Pin ConfigurationsPower Supply Inputs to the Device Pin DefinitionsHardware Store HSB Operation Device OperationAutoStore Operation Software Store Hardware Recall Power UpSoftware Recall Data ProtectionCurrent versus Cycle Time Low Average Active Power Best PracticesRead Sram Mode Selection A15 A0 PowerWrite Sram StoreReal Time Clock Operation Calibrating the Clock AlarmWatchdog Timer Interrupts Power MonitorInterrupt Register Flags RegisterRecommended Values Interrupt Block DiagramWDF Oscf RTC Register Map5 BCD Format Data Function/RangeTime Keeping Months 0x1FFFE 10s Month Register Map Detail Time Keeping Years 0x1FFFF 10s YearsDate Time Keeping Hours 0x1FFFB Time Keeping Minutes 0x1FFFARegister Map Detail Calibration/Control Alarm Day 0x1FFF50x1FFF7 Interrupt Status/Control 0x1FFF6When the Flags register is read or on power-up Register Map Detail Alarm Hours 0x1FFF4 10s Alarm HoursTo ignore the hours value Alarm Minutes 0x1FFF3 Range Ambient Temperature DC Electrical CharacteristicsMaximum Ratings Operating RangeCapacitance Data Retention and EnduranceThermal Resistance AC Test ConditionsParameter Sram Read Cycle AC Switching CharacteristicsParameter Sram Write Cycle Min MaxParameter Description CY14B101K Unit Min Max AutoStore or Power Up RecallParameter Alt Description 25 ns 35 ns 45 ns Unit Min Max Software Controlled STORE/RECALL Cycles 21Hardware Store Cycle Soft Sequence CommandsTruth Table For Sram Operations RTC CharacteristicsInputs and Outputs Mode Power Nvsram Part Numbering Nomenclature CY 14 B 101 K SP 25 X C TOrdering Information Pin Shrunk Small Outline Package Package DiagramsOrig. of Change Submission Description of Change Date Document History2663934 Updated FeaturesUSB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions
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