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| CY14B101K | |
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Hardware STORE Cycle |
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Parameter | Alt. |
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| Description |
| CY14B101K |
| Unit | |
Parameter |
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| Min |
| Max |
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tDELAY [25] |
| Time Allowed to Complete SRAM Cycle | 1 |
| 70 |
| μs | ||
tPHSB | tHLHX | Hardware STORE Pulse Width | 15 |
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| ns |
Figure 15. Hardware STORE Cycle
+6%,1
+6%287
W3+6%+/+;
W+/%/
W6725(
+,*+,03('$1&(
+,*+,03('$1&(
W'(/$<
'4'$7$287'$7$9$/,'
'$7$9$/,'
Soft Sequence Commands
Parameter | Description |
| CY14B101K | Unit | |
Min |
| Max | |||
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tSS [22, 24] | Soft Sequence Processing Time |
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| 70 | μs |
Figure 16. Soft Sequence Processing [22, 24]
| 6RIW6HTXHQFH | W66 | 6RIW6HTXHQFH | W66 | ||
| &RPPDQG |
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| &RPPDQG |
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$GGUHVV | $GGUHVV | $GGUHVV | $GGUHVV | $GGUHVV |
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| W6$ |
| W&: |
| W&: |
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&( |
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9&& |
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Notes
23.This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
24.Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See specific command.
25.Read and Write cycles in progress before HSB are given this amount of time to complete.
Document Number: | Page 21 of 28 |
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