Cypress CY14B101K manual AC Switching Characteristics, Parameter Sram Read Cycle

Page 17

CY14B101K

AC Switching Characteristics

Parameter

Description

25 ns

35 ns

45 ns

Unit

Cypress

Alt.

Min

Max

Min

Max

Min

Max

Parameter

Parameter

 

 

 

 

 

 

 

 

 

 

SRAM Read

Cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tACE

tELQV

Chip Enable Access Time

 

25

 

35

 

45

ns

tRC [11]

tAVAV, tELEH

Read Cycle Time

25

 

35

 

45

 

ns

tAA [12]

tAVQV

Address Access Time

 

25

 

35

 

45

ns

tDOE

tGLQV

Output Enable to Data Valid

 

12

 

15

 

20

ns

tOHA [12]

tAXQX

Output Hold After Address Change

3

 

3

 

3

 

ns

tLZCE [13]

tELQX

Chip Enable to Output Active

3

 

3

 

3

 

ns

tHZCE [13]

tEHQZ

Chip Disable to Output Inactive

 

10

 

13

 

15

ns

tLZOE [13]

tGLQX

Output Enable to Output Active

0

 

0

 

0

 

ns

tHZOE [13]

tGHQZ

Output Disable to Output Inactive

 

10

 

13

 

15

ns

tPU [14]

tELICCH

Chip Enable to Power Active

0

 

0

 

0

 

ns

tPD [14]

tEHICCL

Chip Disable to Power Standby

 

25

 

35

 

45

ns

Figure 8. SRAM Read Cycle 1: Address Controlled [11, 12, 15]

$''5(66

W5&

W$$

W2+$

'4 '$7$287

'$7$9$/,'

Figure 9. SRAM Read Cycle 2: CE and OE Controlled [11, 15]

$''5(66

&(

2(

'4 '$7$287

,&&

W5&

W$&(

W/=&(

W'2(

W/=2(

W38 $&7,9(

67$1'%<

W3'

W+=&(

W+=2(

'$7$9$/,'

Notes

11.WE is HIGH during SRAM Read Cycles.

12.Device is continuously selected with CE and OE both Low.

13.Measured ±200 mV from steady state output voltage.

14.These parameters are guaranteed by design and are not tested.

15.HSB must remain HIGH during READ and WRITE cycles.

Document Number: 001-06401 Rev. *I

Page 17 of 28

[+] Feedback

Image 17
Contents Logic Block Diagram FeaturesFunctional Description Cypress Semiconductor Corporation 198 Champion CourtOutput Enable, Active LOW. The active low Pin ConfigurationsPower Supply Inputs to the Device Pin DefinitionsHardware Store HSB Operation Device OperationAutoStore Operation Software Store Hardware Recall Power UpSoftware Recall Data ProtectionCurrent versus Cycle Time Low Average Active Power Best PracticesRead Sram Mode Selection A15 A0 PowerWrite Sram StoreReal Time Clock Operation Calibrating the Clock AlarmWatchdog Timer Interrupts Power MonitorInterrupt Register Flags RegisterRecommended Values Interrupt Block DiagramWDF Oscf RTC Register Map5 BCD Format Data Function/RangeTime Keeping Months 0x1FFFE 10s Month Register Map Detail Time Keeping Years 0x1FFFF 10s YearsDate Time Keeping Hours 0x1FFFB Time Keeping Minutes 0x1FFFARegister Map Detail Calibration/Control Alarm Day 0x1FFF50x1FFF7 Interrupt Status/Control 0x1FFF6When the Flags register is read or on power-up Register Map Detail Alarm Hours 0x1FFF4 10s Alarm HoursTo ignore the hours value Alarm Minutes 0x1FFF3 Range Ambient Temperature DC Electrical CharacteristicsMaximum Ratings Operating RangeCapacitance Data Retention and EnduranceThermal Resistance AC Test ConditionsParameter Sram Read Cycle AC Switching CharacteristicsParameter Sram Write Cycle Min MaxParameter Description CY14B101K Unit Min Max AutoStore or Power Up RecallParameter Alt Description 25 ns 35 ns 45 ns Unit Min Max Software Controlled STORE/RECALL Cycles 21Hardware Store Cycle Soft Sequence CommandsTruth Table For Sram Operations RTC CharacteristicsInputs and Outputs Mode Power Nvsram Part Numbering Nomenclature CY 14 B 101 K SP 25 X C TOrdering Information Pin Shrunk Small Outline Package Package DiagramsOrig. of Change Submission Description of Change Date Document History2663934 Updated FeaturesUSB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions