Cypress CY7C138, CY7C139 Non-Contending Read/Write Inputs Outputs Operation, Right Port Function

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CY7C138, CY7C139

Table 3. Non-Contending Read/Write

Inputs

Outputs

Operation

CE

R/W

OE

SEM

I/O0-7/8

H

X

X

H

High Z

Power-Down

H

H

L

L

Data Out

Read Data in Semaphore

X

X

H

X

High Z

I/O Lines Disabled

H

X

L

Data In

Write to Semaphore

L

H

L

H

Data Out

Read

L

L

X

H

Data In

Write

L

X

X

L

Illegal Condition

Table 4. Interrupt Operation Example (assumes

BUSY

L

=BUSY

R=HIGH)

Left Port

Right Port

Function

R/W

CE

OE

A0-11

INT

R/W

CE

OE

A0-11

INT

Set Left

X

X

X

X

L

L

L

X

FFE

X

INT

Reset Left

X

L

L

FFE

H

X

X

X

X

X

INT

Set Right

L

L

X

FFF

X

X

X

X

X

L

INT

Reset Right

X

X

X

X

X

X

L

L

FFF

H

INT

Table 5. Semaphore Operation Example

Function

I/O0-7/8Left

I/O0-7/8Right

Status

No action

1

1

Semaphore free

Left port writes semaphore

0

1

Left port obtains semaphore

Right port writes 0 to semaphore

0

1

Right side is denied access

Left port writes 1 to semaphore

1

0

Right port is granted access to semaphore

Left port writes 0 to semaphore

1

0

No change. Left port is denied access

Right port writes 1 to semaphore

0

1

Left port obtains semaphore

Left port writes 1 to semaphore

1

1

No port accessing semaphore address

Right port writes 0 to semaphore

1

0

Right port obtains semaphore

Right port writes 1 to semaphore

1

1

No port accessing semaphore

Left port writes 0 to semaphore

0

1

Left port obtains semaphore

Left port writes 1 to semaphore

1

1

No port accessing semaphore

Document #: 38-06037 Rev. *D

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Contents Functional Description FeaturesLogic Block Diagram Cypress Semiconductor Corporation 198 Champion CourtSelection Guide Description Pin ConfigurationsPin Definitions Left Port Right Port Description UnitMaximum Ratings Electrical Characteristics Over the Operating RangeTemperature Operating RangeCapacitance8 Parameter Description Test Conditions Max UnitGND Switching Characteristics Over the Operating Range9Output ALL Input PulsesBusy Switching WaveformsTiming Data OUTData INR Valid Address L Match Data OUT Data ValidAddress R Match Data Outl ValidHigh Impedance Address SEM or CEData Data Valid AddressDataout Valid Valid AddressSEM Write Cycle Read CycleAddressl Match Addressr MatchData INR Valid BusylAddress L Addressr Busyr Address L,R Address Match CEL CER BusyrADDRESSL,R CER CEL Busy L Address Match Address MismatchLeft Side Clears Intl Right Side Clears INT RRight Side Sets Intl Architecture Write OperationRight Port Function Non-Contending Read/Write Inputs Outputs OperationInterrupt Operation Example assumes Output Source Current Supply Voltage Ambient Temperature C Output VoltageNormalized Supply Current NormalizedSpeed Ordering Code Package DiagramOrdering Information Package Type OperatingSales, Solutions and Legal Information Document History

CY7C138, CY7C139 specifications

The Cypress CY7C139 and CY7C138 are advanced static random-access memory (SRAM) components that have garnered attention in the field of digital electronics due to their high performance and reliability. These SRAMs are designed to meet the demanding needs of a variety of applications, ranging from telecommunications to automotive systems and consumer electronics.

The CY7C139 is a 128K x 8 bit static RAM, while the CY7C138 is a 256K x 8 bit SRAM, offering flexible memory solutions for designers. Both devices utilize a fast access time, typically around 10 to 15 nanoseconds, allowing quick data retrieval essential for high-speed applications. This remarkable speed is complemented by low power consumption, making them suitable for battery-operated devices and other applications where efficiency is paramount.

One of the key features of the CY7C139 and CY7C138 is their asynchronous operation, which enables them to provide high-speed data access without the need for a clock signal. This characteristic simplifies system design and enhances performance, as users can write to and read from the memory without waiting for synchronization. The devices support standard CMOS interface levels, which facilitate integration into a diverse range of digital systems.

Additionally, these SRAMs have been designed with a low standby current, making them particularly effective for low-power applications. The devices also include a robust input/output structure that ensures reliable signal integrity under various operating conditions. Their built-in data retention capability allows the SRAMs to retain stored data even during power failures, a critical feature in many systems that require data preservation.

Both CY7C139 and CY7C138 SRAMs support a wide range of temperature and voltage ranges, making them suitable for industrial and automotive environments. They are packaged in industry-standard configurations, allowing for easy integration into existing designs.

In summary, the Cypress CY7C139 and CY7C138 SRAMs provide high-speed, low-power memory solutions suitable for various applications. Their asynchronous operation, low standby current, and robust performance characteristics make them a preferred choice for engineers looking to enhance system efficiency and reliability. These features make the CY7C139 and CY7C138 indispensable components in modern digital electronic designs.