Cypress CY7C138 manual Pin Configurations, Pin Definitions Left Port Right Port Description, Unit

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CY7C138, CY7C139

Pin Configurations

Figure 1. 68-Pin PLCC (Top View)

\

1L

0L

[4]

I/O

I/O

NC

OE L

R/WL

 

L L

CC

11L 10L

9L

8L 7L 6L

 

 

SEM

 

 

CE

NC NC V

NC A A

A

A A A

I/O2L

 

9

8

7

6

5

4

3

2

1 68

67 66 65 64 63 62 61

 

 

A5L

 

 

 

 

10

 

 

 

 

 

 

 

 

 

60

 

 

I/O3L

 

11

 

 

 

 

 

 

 

 

 

59

 

 

A4L

I/O4L

 

12

 

 

 

 

 

 

 

 

 

58

 

 

A

I/O5L

 

 

 

 

 

 

 

 

 

 

 

 

3L

 

13

 

 

 

 

 

 

 

 

 

57

 

 

A2L

GND

 

14

 

 

 

 

 

 

 

 

 

56

 

 

A1L

I/O6L

 

15

 

 

 

 

 

 

 

 

 

55

 

 

A0L

I/O7L

 

16

 

 

 

 

 

 

 

 

 

54

 

 

INT

L

VCC

 

17

 

 

 

 

 

 

CY7C138/9

53

 

 

BUSY

L

GND

 

18

 

 

 

 

 

 

 

 

 

52

 

 

GND

 

 

 

 

 

 

 

 

 

 

 

I/O0R

 

19

 

 

 

 

 

 

 

 

 

51

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M/S

 

 

 

 

 

 

 

 

 

 

 

I/O1R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

 

20

 

 

 

 

 

 

 

 

 

50

 

 

BUSY

 

 

 

 

 

 

 

 

 

 

 

I/O2R

 

21

 

 

 

 

 

 

 

 

 

49

 

 

INT

R

 

 

 

 

 

 

 

 

 

 

 

VCC

 

22

 

 

 

 

 

 

 

 

 

48

 

 

A

I/O3R

 

 

 

 

 

 

 

 

 

 

 

 

 

0R

 

23

 

 

 

 

 

 

 

 

 

47

 

 

A1R

 

 

 

 

 

 

 

 

 

 

 

 

I/O4R

 

24

 

 

 

 

 

 

 

 

 

46

 

 

A2R

 

 

 

 

 

 

 

 

 

 

 

 

I/O5R

 

25

 

 

 

 

 

 

 

 

 

45

 

 

A3R

 

 

 

 

 

 

 

 

 

 

 

 

I/O6R

 

26

 

 

 

 

 

 

 

 

 

44

 

 

A4R

 

 

2728

29 30 3132

33 34 35 36 37 38 39 40 41 42 43

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7R

[3]

I/O

NC

OER

R/W R SEM R

 

R

11R

10R

9R

8R

7R

6R

5R

 

 

CE

NC NC GND NC A A

A A

A A A

 

 

 

 

 

 

 

Table 1. Pin Definitions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Left Port

 

 

 

Right Port

 

 

 

 

Description

 

 

 

I/O0L–7L(8L)

 

I/O0R–7R(8R)

 

Data Bus Input/Output

 

 

 

 

 

A0L–11L

 

A0R–11R

 

Address Lines

 

 

 

 

 

 

CEL

 

CER

 

Chip Enable

 

 

 

 

 

 

OEL

 

OER

 

Output Enable

 

 

 

 

 

 

R/WL

 

R/WR

 

Read/Write Enable

 

 

 

 

 

 

SEML

 

SEMR

 

Semaphore Enable. When asserted LOW, allows access to eight

 

 

 

 

 

 

 

 

 

semaphores. The three least significant bits of the address lines will

 

 

 

 

 

 

 

 

determine which semaphore to write or read. The I/O0 pin is used when

 

 

 

 

 

 

 

 

writing to a semaphore. Semaphores are requested by writing a 0 into the

 

 

 

 

 

 

 

 

respective location.

 

 

 

 

 

 

INT

L

 

INT

R

 

Interrupt Flag. INTL is set when right port writes location FFE and is cleared

 

 

 

 

 

 

 

 

when left port reads location FFE. INTR is set when left port writes location

 

 

 

 

 

 

 

 

FFF and is cleared when right port reads location FFF.

 

BUSY

L

 

BUSY

R

 

Busy Flag

 

 

 

 

 

 

M/S

 

 

 

 

 

Master or Slave Select

 

 

 

 

 

VCC

 

 

 

 

 

Power

 

 

 

 

 

 

GND

 

 

 

 

 

Ground

 

 

 

 

 

 

Table 2. Selection Guide

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Description

 

 

7C138-15

 

7C138-25

 

7C138-35

7C138-55

 

Unit

 

 

 

 

7C139-15

 

7C139-25

 

7C139-35

7C139-55

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Maximum Access Time (ns)

 

 

15

 

25

 

35

55

 

ns

Maximum Operating Current

Commercial

 

220

 

180

 

160

160

 

mA

Maximum Standby Current for ISB1

Commercial

 

60

 

40

 

30

30

 

mA

Notes

 

 

 

 

 

 

 

 

 

 

 

 

 

3.I/O8R on the CY7C139.

4.I/O8L on the CY7C139.

Document #: 38-06037 Rev. *D

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Contents Functional Description FeaturesLogic Block Diagram Cypress Semiconductor Corporation 198 Champion CourtSelection Guide Description Pin ConfigurationsPin Definitions Left Port Right Port Description UnitMaximum Ratings Electrical Characteristics Over the Operating RangeTemperature Operating RangeCapacitance8 Parameter Description Test Conditions Max UnitGND Switching Characteristics Over the Operating Range9Output ALL Input PulsesBusy Switching WaveformsTiming Data OUTData INR Valid Address L Match Data OUT Data ValidAddress R Match Data Outl ValidHigh Impedance Address SEM or CEData Data Valid AddressDataout Valid Valid AddressSEM Write Cycle Read CycleAddressl Match Addressr MatchData INR Valid BusylAddress L Addressr Busyr Address L,R Address Match CEL CER BusyrADDRESSL,R CER CEL Busy L Address Match Address MismatchLeft Side Clears Intl Right Side Clears INT RRight Side Sets Intl Architecture Write OperationRight Port Function Non-Contending Read/Write Inputs Outputs OperationInterrupt Operation Example assumes Output Source Current Supply Voltage Ambient Temperature C Output VoltageNormalized Supply Current NormalizedSpeed Ordering Code Package DiagramOrdering Information Package Type OperatingSales, Solutions and Legal Information Document History

CY7C138, CY7C139 specifications

The Cypress CY7C139 and CY7C138 are advanced static random-access memory (SRAM) components that have garnered attention in the field of digital electronics due to their high performance and reliability. These SRAMs are designed to meet the demanding needs of a variety of applications, ranging from telecommunications to automotive systems and consumer electronics.

The CY7C139 is a 128K x 8 bit static RAM, while the CY7C138 is a 256K x 8 bit SRAM, offering flexible memory solutions for designers. Both devices utilize a fast access time, typically around 10 to 15 nanoseconds, allowing quick data retrieval essential for high-speed applications. This remarkable speed is complemented by low power consumption, making them suitable for battery-operated devices and other applications where efficiency is paramount.

One of the key features of the CY7C139 and CY7C138 is their asynchronous operation, which enables them to provide high-speed data access without the need for a clock signal. This characteristic simplifies system design and enhances performance, as users can write to and read from the memory without waiting for synchronization. The devices support standard CMOS interface levels, which facilitate integration into a diverse range of digital systems.

Additionally, these SRAMs have been designed with a low standby current, making them particularly effective for low-power applications. The devices also include a robust input/output structure that ensures reliable signal integrity under various operating conditions. Their built-in data retention capability allows the SRAMs to retain stored data even during power failures, a critical feature in many systems that require data preservation.

Both CY7C139 and CY7C138 SRAMs support a wide range of temperature and voltage ranges, making them suitable for industrial and automotive environments. They are packaged in industry-standard configurations, allowing for easy integration into existing designs.

In summary, the Cypress CY7C139 and CY7C138 SRAMs provide high-speed, low-power memory solutions suitable for various applications. Their asynchronous operation, low standby current, and robust performance characteristics make them a preferred choice for engineers looking to enhance system efficiency and reliability. These features make the CY7C139 and CY7C138 indispensable components in modern digital electronic designs.