Cypress CY7C1570V18, CY7C1577V18 Capacitance, Thermal Resistance, AC Electrical Characteristics

Page 21

CY7C1566V18, CY7C1577V18

CY7C1568V18, CY7C1570V18

Electrical Characteristics

Over the Operating Range [13]

DC Electrical Characteristics

Parameter

Description

Test Conditions

 

Min

Typ

Max

Unit

ISB1

Automatic Power down

Max VDD,

400MHz

(x8)

 

 

550

mA

 

Current

Both Ports Deselected,

 

 

 

 

 

 

 

 

(x9)

 

 

550

 

 

 

VIN VIH or VIN VIL

 

 

 

 

 

 

 

(x18)

 

 

550

 

 

 

f = fMAX = 1/tCYC,

 

 

 

 

 

 

Inputs Static

 

(x36)

 

 

550

 

 

 

 

375MHz

(x8)

 

 

525

mA

 

 

 

 

(x9)

 

 

525

 

 

 

 

 

(x18)

 

 

525

 

 

 

 

 

(x36)

 

 

525

 

 

 

 

333MHz

(x8)

 

 

500

mA

 

 

 

 

(x9)

 

 

500

 

 

 

 

 

(x18)

 

 

500

 

 

 

 

 

(x36)

 

 

500

 

 

 

 

300MHz

(x8)

 

 

450

mA

 

 

 

 

(x9)

 

 

450

 

 

 

 

 

(x18)

 

 

450

 

 

 

 

 

(x36)

 

 

450

 

AC Electrical Characteristics

Over the Operating Range [15]

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

VIH

Input HIGH Voltage

 

VREF + 0.2

VDDQ + 0.24

V

VIL

Input LOW Voltage

 

–0.24

VREF – 0.2

V

Capacitance

Tested initially and after any design or process change that may affect these parameters.

Parameter

Description

Test Conditions

Max

Unit

CIN

Input Capacitance

TA = 25°C, f = 1 MHz, VDD = 1.8V, VDDQ = 1.5V

5.5

pF

CCLK

Clock Input Capacitance

 

8.5

pF

CO

Output Capacitance

 

8

pF

Thermal Resistance

Tested initially and after any design or process change that may affect these parameters.

Parameter

Description

Test Conditions

165 FBGA

Unit

Package

 

 

 

 

ΘJA

Thermal Resistance

Test conditions follow standard test methods and

11.82

°C/W

 

(Junction to Ambient)

procedures for measuring thermal impedance, in

 

 

 

 

accordance with EIA/JESD51.

 

 

ΘJC

Thermal Resistance

2.33

°C/W

 

 

(Junction to Case)

 

 

 

Document Number: 001-06551 Rev. *E

Page 21 of 28

[+] Feedback

Image 21
Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1577V18 Logic Block Diagram CY7C1566V18Logic Block Diagram CY7C1570V18 Logic Block Diagram CY7C1568V18Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1566V18 8M x CY7C1577V18 8M xCY7C1570V18 2M x CY7C1568V18 4M xPin Definitions Pin Name Pin DescriptionSynchronous Read/Write Input. When Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Application Example Valid Data Indicator QvldEcho Clocks SRAM#1 SRAM#2Write Cycle Descriptions OperationComments Write cycle description table for CY7C1570V18 follows Write cycle description table for CY7C1577V18 followsDevice Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit Number Bump ID Boundary Scan OrderPower Up Waveforms Power Up Sequence in DDR-II+ SramPower Up Sequence DLL ConstraintsDC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Range AmbientCapacitance AC Electrical CharacteristicsThermal Resistance Parameter Description Test Conditions Max UnitAC Test Loads and Waveforms AC Test Loads and WaveformsParameter Min Max Switching CharacteristicsHigh LOWRead/Write/Deselect Sequence 29, 30 Switching WaveformsNOP Read NOP WriteOrdering Information CY7C1566V18, CY7C1577V18 Ball Fbga 15 x 17 x 1.4 mm Package DiagramDocument History ECN No Issue Orig. Description of Change DateNXR IGS