Cypress CY7C1566V18 manual TDO for Jtag, TCK Pin for Jtag, TDI Pin for Jtag, TMS Pin for Jtag

Page 7

 

 

 

 

 

 

CY7C1566V18, CY7C1577V18

 

 

 

 

 

 

CY7C1568V18, CY7C1570V18

 

 

 

 

 

 

Pin Definitions (continued)

 

 

 

 

 

 

 

Pin Name

IO

 

 

Pin Description

 

 

 

 

 

ZQ

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus

 

 

 

 

impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected

 

 

 

 

between ZQ and ground. Alternatively, this pin is connected directly to VDDQ that enables the minimum

 

 

 

 

impedance mode. This pin is not connected directly to GND or is left unconnected.

 

 

 

 

 

 

 

 

Input

DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing

 

DOFF

 

 

 

 

in the DLL turned off operation is different from that listed in this datasheet. For normal operation, this pin

 

 

 

 

is connected to a pull up through a 10 Kohm or less pull up resistor. The device behaves in DDR-I mode

 

 

 

 

when the DLL is turned off. In this mode, the device is operated at a frequency of up to 167 MHz with

 

 

 

 

DDR-I timing.

 

 

 

 

 

TDO

Output

TDO for JTAG.

 

 

 

 

 

TCK

Input

TCK Pin for JTAG.

 

 

 

 

 

TDI

Input

TDI Pin for JTAG.

 

 

 

 

 

TMS

Input

TMS Pin for JTAG.

 

 

 

 

 

NC

N/A

Not Connected to the Die. Is tied to any voltage level.

 

 

 

 

 

NC/144M

N/A

Not Connected to the Die. Is tied to any voltage level.

 

 

 

 

 

NC/288M

N/A

Not Connected to the Die. Is tied to any voltage level.

 

 

 

 

 

VREF

Input

Reference Voltage Input. Static input is used to set the reference level for HSTL inputs, outputs, and AC

 

 

 

Reference

measurement points.

 

 

 

 

 

VDD

Power Supply

Power Supply Inputs to the Core of the Device.

 

VSS

Ground

Ground for the Device.

 

VDDQ

Power Supply

Power Supply Inputs for the Outputs of the Device.

Document Number: 001-06551 Rev. *E

Page 7 of 28

[+] Feedback

Page 6 Page 8
Image 7
Page 6 Page 8
Contents Selection Guide FeaturesConfigurations Functional DescriptionLogic Block Diagram CY7C1577V18 Logic Block Diagram CY7C1566V18Logic Block Diagram CY7C1570V18 Logic Block Diagram CY7C1568V18CY7C1577V18 8M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1566V18 8M xCY7C1570V18 2M x CY7C1568V18 4M xPin Name Pin Description Pin DefinitionsSynchronous Read/Write Input. When TCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagFunctional Overview SRAM#1 SRAM#2 Valid Data Indicator QvldApplication Example Echo ClocksOperation Write Cycle DescriptionsComments Into the device. D359 remains unaltered Write cycle description table for CY7C1577V18 followsWrite cycle description table for CY7C1570V18 follows DeviceIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit Number Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in DDR-II+ SramPower Up Waveforms Power Up SequenceRange Ambient Electrical CharacteristicsDC Electrical Characteristics Maximum RatingsParameter Description Test Conditions Max Unit AC Electrical CharacteristicsCapacitance Thermal ResistanceAC Test Loads and Waveforms AC Test Loads and WaveformsLOW Switching CharacteristicsParameter Min Max HighRead NOP Write Switching WaveformsRead/Write/Deselect Sequence 29, 30 NOPOrdering Information CY7C1566V18, CY7C1577V18 Ball Fbga 15 x 17 x 1.4 mm Package DiagramIGS ECN No Issue Orig. Description of Change DateDocument History NXR
Top Page Image Contents