Cypress CY7C1570V18, CY7C1577V18, CY7C1568V18, CY7C1566V18 manual Ordering Information

Page 25

CY7C1566V18, CY7C1577V18

CY7C1568V18, CY7C1570V18

Ordering Information

Not all of the speed, package, and temperature ranges are available. Contact your local sales representative or visit www.cypress.com for actual products offered.

	Speed		Package	Package Type	Operating
	(MHz)	Ordering Code	Diagram	Package Type	Range
	(MHz)	Ordering Code	Diagram		Range
	400	CY7C1566V18-400BZC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Commercial

		CY7C1577V18-400BZC

		CY7C1568V18-400BZC

		CY7C1570V18-400BZC

		CY7C1566V18-400BZXC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

		CY7C1577V18-400BZXC

		CY7C1568V18-400BZXC

		CY7C1570V18-400BZXC

		CY7C1566V18-400BZI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Industrial

		CY7C1577V18-400BZI

		CY7C1568V18-400BZI

		CY7C1570V18-400BZI

		CY7C1566V18-400BZXI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

		CY7C1577V18-400BZXI

		CY7C1568V18-400BZXI

		CY7C1570V18-400BZXI

	375	CY7C1566V18-375BZC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Commercial

		CY7C1577V18-375BZC

		CY7C1568V18-375BZC

		CY7C1570V18-375BZC

		CY7C1566V18-375BZXC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

		CY7C1577V18-375BZXC

		CY7C1568V18-375BZXC

		CY7C1570V18-375BZXC

		CY7C1566V18-375BZI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Industrial

		CY7C1577V18-375BZI

		CY7C1568V18-375BZI

		CY7C1570V18-375BZI

		CY7C1566V18-375BZXI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

		CY7C1577V18-375BZXI

		CY7C1568V18-375BZXI

		CY7C1570V18-375BZXI

Document Number: 001-06551 Rev. *E

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1577V18 Logic Block Diagram CY7C1566V18Logic Block Diagram CY7C1570V18 Logic Block Diagram CY7C1568V18Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1566V18 8M x CY7C1577V18 8M xCY7C1570V18 2M x CY7C1568V18 4M xPin Name Pin Description Pin DefinitionsSynchronous Read/Write Input. When Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Application Example Valid Data Indicator QvldEcho Clocks SRAM#1 SRAM#2Operation Write Cycle DescriptionsComments Write cycle description table for CY7C1570V18 follows Write cycle description table for CY7C1577V18 followsDevice Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit Number Bump ID Boundary Scan OrderPower Up Waveforms Power Up Sequence in DDR-II+ SramPower Up Sequence DLL ConstraintsDC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Range AmbientCapacitance AC Electrical CharacteristicsThermal Resistance Parameter Description Test Conditions Max UnitAC Test Loads and Waveforms AC Test Loads and WaveformsParameter Min Max Switching CharacteristicsHigh LOWRead/Write/Deselect Sequence 29, 30 Switching WaveformsNOP Read NOP WriteOrdering Information CY7C1566V18, CY7C1577V18 Ball Fbga 15 x 17 x 1.4 mm Package DiagramDocument History ECN No Issue Orig. Description of Change DateNXR IGS