Pin Definitions, Pin Name Pin Description

CY7C1566V18, CY7C1577V18

CY7C1568V18, CY7C1570V18

Pin Definitions

Pin Name

Pin Description

DQ[x:0]

Input and

Data Input and Output Signals. Inputs are sampled on the rising edge of K and

clocks during valid

Output

write operations. These pins drive out the requested data during a read operation. Valid data is driven out

Synchronous

on the rising edge of both the K and K clocks during read operations. When read access is deselected,

Q[x:0] are automatically tri-stated.

CY7C1566V18 − DQ[7:0]

CY7C1577V18 − DQ[8:0]

CY7C1568V18 − DQ[17:0]

CY7C1570V18 − DQ[35:0]

Input

Synchronous Load. Sampled on the rising edge of the K clock. This input is brought LOW when a bus

Synchronous

cycle sequence is defined. This definition includes address and read or write direction. All transactions

operate on a burst of 2 data. LD must meet the setup and hold times around edge of K.

Input

Nibble Write Select 0, 1 − Active LOW (CY7C1566V18 only). Sampled on the rising edge of the K and

NWS

NWS1

Synchronous

K clocks during write operations. Used to select the nibble that is written into the device during the current

portion of the write operations. Nibbles not written remain unaltered.

NWS0 controls D[3:0] and NWS1 controls D[7:4].

All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select

ignores the corresponding nibble of data and does not write into the device.

Input

Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and

clocks during

BWS

BWS1,

Synchronous

write operations. Used to select which byte is written into the device during the current portion of the write

BWS2,

operations. Bytes not written remain unaltered.

BWS

CY7C1577V18 −

BWS

controls D

[8:0]

CY7C1568V18 − BWS0

controls D[8:0] and BWS1 controls D[17:9].

CY7C1570V18 − BWS0

controls D[8:0], BWS1 controls D[17:9],

BWS2 controls D[26:18] and BWS3 controls D[35:27].

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select

ignores the corresponding byte of data and does not write into the device.

Input

Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These

Synchronous

address inputs are multiplexed for both read and write operations. Internally, the device is organized as

8M x 8 (2 arrays each of 4M x 8) for CY7C1566V18, 8M x 9 (2 arrays each of 4M x 9) for CY7C1577V18,

4M x 18 (2 arrays each of 2M x 18) for CY7C1568V18, and 2M x 36 (2 arrays each of 1M x 36) for

CY7C1570V18.

Input

Synchronous Read/Write Input. When

is LOW, this input designates the access type (read when

R/W

Synchronous

R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times

around edge of K.

QVLD

Valid Output

Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and

CQ.

Indicator

Input Clock

Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device

and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising

edge of K.

KInput Clock Negative Input Clock Input. K is used to capture synchronous data presented to the device and to drive out data through Q[x:0] when in single clock mode.

CQ	Clock Output	Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
		(K) of the DDR-II+. The timing for the echo clocks is shown in Switching Characteristics on page 23.

	Clock Output	Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
CQ	Clock Output
		(K) of the DDR-II+. The timing for the echo clocks is shown in Switching Characteristics on page 23.

Document Number: 001-06551 Rev. *E

Page 6 of 28

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