Cypress CY7C1350G Switching Waveforms, Read/Write Timing19, 20, Cen, Address A1 A2, DON’T Care

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CY7C1350G

Switching Waveforms

tCES tCEH

BW[A:D]

A3	A4	A5
	tCO

A6 A7

tAS tAH

tDS tDH

tCLZ

tDOH

tOEV tCHZ

Data

D(A1)

D(A2) D(A2+1) Q(A3) Q(A4)

tOEHZ

Q(A4+1) D(A5)

tDOH tOELZ

Q(A6)

DESELECT

Notes:

19.For this waveform ZZ is tied LOW.

20.When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

21.Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.

Document #: 38-05524 Rev. *F

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram Champion Court San Jose , CA Document # 38-05524 Rev. *FCY7C1350G Pin ConfigurationsSelection Guide 250 MHz 200 MHz 166 MHz 133 MHz 100 MHz UnitName Description Pin Configurations Ball BGA PinoutPin Definitions Byte Write Inputs, active LOW . Qualified withFunctional Overview Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDOperation Address Used ZZ Mode Electrical CharacteristicsPartial Truth Table for Read/Write 2, 3 FunctionOperating Range Electrical Characteristics Over the Operating Range10Maximum Ratings Ambient RangeAC Test Loads and Waveforms Capacitance12Thermal Resistance Parameter Description Test Conditions Tqfp 119 BGA Unit MaxSwitching Characteristics Over the Operating Range17 CEN Switching WaveformsRead/Write Timing19, 20 Address A1 A2ZZ Mode Timing23 NOP, STALL, and Deselect Cycles19, 20Ordering Information Package Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Issue Orig. Description of Change Date Document History