Cypress CY7C1350G manual Pin Configurations Ball BGA Pinout, Pin Definitions, Name Description

CY7C1350G

Pin Configurations (continued)

119-Ball BGA Pinout

1

2

3

4

5

6

7

A

VDDQ

A

A

NC/18M

A

A

VDDQ

B

NC/576M

CE2

A

A

NC

ADV/LD

CE3

C

NC/1G

A

A

VDD

A

A

NC

D

DQC

DQPC

VSS

NC

VSS

DQPB

DQB

E

DQC

DQC

VSS

1

VSS

DQB

DQB

CE

F

VDDQ

DQC

VSS

VSS

DQB

VDDQ

OE

G

DQC

DQC

C

NC/9M

B

DQB

DQB

BW

BW

H

DQC

DQC

VSS

VSS

DQB

DQB

WE

J

VDDQ

VDD

VSS

VDD

VSS

VDD

VDDQ

K

DQD

DQD

VSS

CLK

VSS

DQA

DQA

L

DQD

DQD

D

NC

DQA

DQA

BW

BW

A

M

VDDQ

DQD

VSS

VSS

DQA

VDDQ

CEN

N

DQD

DQD

VSS

A1

VSS

DQA

DQA

P

DQD

DQPD

VSS

A0

VSS

DQPA

DQA

R

NC/144M

A

MODE

VDD

NC

A

NC/288M

T

NC

NC/72M

A

A

A

NC/36M

ZZ

U

VDDQ

NC

NC

NC

NC

NC

VDDQ

Pin Definitions

Name			I/O	Description
A0, A1, A			Input-	Address Inputs used to select one of the 128K address locations. Sampled at the rising edge
			Synchronous	of the CLK. A[1:0] are fed to the two-bit burst counter.
		[A:D]	Input-	Byte Write Inputs, active LOW. Qualified with		to conduct writes to the SRAM. Sampled on
BW					WE
			Synchronous	the rising edge of CLK.
			Input-	Write Enable Input, active LOW. Sampled on the rising edge of CLK if				is active LOW. This
WE							CEN
			Synchronous	signal must be asserted LOW to initiate a write sequence.
			Input-	Advance/Load Input. Used to advance the on-chip address counter or load a new address. When
ADV/LD
			Synchronous	HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new
				address can be loaded into the device for an access. After being deselected, ADV/LD should be
				driven LOW in order to load a new address.
CLK			Input-Clock	Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with
									CEN.
				CLK is only recognized if CEN is active LOW.
	1		Input-	Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
			Synchronous	CE2 and CE3 to select/deselect the device.
CE2			Input-	Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
			Synchronous	CE1 and CE3 to select/deselect the device.
	3		Input-	Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
			Synchronous	CE1 and CE2 to select/deselect the device.
			Input-	Output Enable, asynchronous input, active LOW. Combined with the synchronous logic block
OE
			Asynchronous	inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
				behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins.						OE
				is masked during the data portion of a write sequence, during the first clock when emerging from
				a deselected state, when the device has been deselected.
			Input-	Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the
CEN
			Synchronous	SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not
				deselect the device, CEN can be used to extend the previous cycle when required.

Document #: 38-05524 Rev. *F Page 3 of 15

[+] Feedback