Cypress CY7C1350G manual Capacitance12, Thermal Resistance, AC Test Loads and Waveforms

CY7C1350G

Electrical Characteristics Over the Operating Range[10, 11] (continued)

Parameter	Description	Test Conditions		Min.	Max.	Unit
ISB3	Automatic CE	VDD = Max, Device Deselected, or	4-ns cycle, 250 MHz		105	mA
	Power-Down	VIN ≤ 0.3V or VIN > VDDQ – 0.3V
			5-ns cycle, 200 MHz		95	mA
	Current—CMOS	f = fMAX = 1/tCYC
			6-ns cycle, 166 MHz		85	mA
	Inputs
			7.5-ns cycle, 133 MHz		75	mA
			10-ns cycle, 100 MHz		65	mA
ISB4	Automatic CE	VDD = Max, Device Deselected,	All speeds		45	mA
	Power-Down	VIN ≥ VIH or VIN ≤ VIL, f = 0
	Current—TTL Inputs

Capacitance[12]

Parameter	Description	Test Conditions	100 TQFP	119 BGA	Unit
			Max.	Max.
CIN	Input Capacitance	TA = 25°C, f = 1 MHz,	5	5	pF
		VDD = 3.3V, VDDQ = 3.3V
CCLK	Clock Input Capacitance		5	5	pF
CI/O	Input/Output Capacitance		5	7	pF
Thermal Resistance[12]

Parameter	Description	Test Conditions	100 TQFP	119 BGA	Unit
			Package	Package
ΘJA	Thermal Resistance (Junction to	Test conditions follow standard	30.32	34.1	°C/W
	Ambient)	test methods and procedures for
		measuring thermal impedance,
Θ	Thermal Resistance (Junction to		6.85	14.0	°C/W
JC	Case)	per EIA/JESD51.

AC Test Loads and Waveforms

3.3V I/O Test Load

OUTPUT Z0 = 50Ω

3.3V		R = 317Ω			ALL INPUT PULSES
OUTPUT				VDDQ
RL = 50Ω				10%		90%
	5 pF		R = 351Ω	GND
				≤ 1 ns

VT = 1.5V

90%

10%

≤ 1 ns

INCLUDING

(c)

(a)

JIG AND

(b)

SCOPE

2.5V I/O Test Load

OUTPUT

2.5V

R = 1667Ω

ALL INPUT PULSES

VDDQ

Z0

= 50Ω

OUTPUT

RL = 50Ω

5 pF

R =1538Ω

GND

10%

90%

VT = 1.25V

≤

1 ns

INCLUDING

(c)

(a)

JIG AND

(b)

SCOPE

90%

10%

≤ 1 ns

Note:

12. Tested initially and after any design or process changes that may affect these parameters.

Document #: 38-05524 Rev. *F Page 8 of 15

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