Cypress CY7C09189V manual Read/Write and Enable Operation34, 35 Inputs Outputs, 0 -I/O Operation

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CY7C09079V/89V/99V

CY7C09179V/89V/99V

Table 1. Read/Write and Enable Operation[34, 35, 36]

 

 

 

 

 

 

 

 

 

 

Inputs

 

 

 

 

 

 

 

 

Outputs

 

 

 

OE

 

CLK

 

 

 

 

 

CE

0

 

CE1

 

R/W

 

 

 

I/O0–I/O9

 

Operation

 

X

 

 

 

 

 

 

 

 

 

H

X

 

X

 

High-Z

 

 

Deselected[37]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X

 

 

 

 

 

 

 

 

 

X

L

 

X

 

High-Z

 

 

Deselected[37]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X

 

 

 

 

 

 

 

 

 

L

H

 

L

 

DIN

 

 

Write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

 

 

 

 

 

 

 

 

L

H

 

H

 

DOUT

 

 

Read[37]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

X

 

 

 

 

 

L

H

 

X

 

High-Z

 

 

Outputs Disabled

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 2. Address Counter Control Operation[34, 38, 39, 40]

 

 

 

 

 

 

Address

Previous

CLK

 

 

 

 

 

CNTRST

 

I/O

 

Mode

 

Operation

ADS

CNTEN

 

 

 

 

 

Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X

X

 

 

 

 

 

 

 

X

X

L

Dout(0)

 

Reset

Counter Reset to Address 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

An

X

 

 

 

 

 

 

 

L

X

H

Dout(n)

 

Load

Address Load into Counter

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X

An

 

 

 

 

 

 

 

H

H

H

Dout(n)

 

Hold

External Address Blocked—Counter

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Disabled

 

X

An

 

 

 

 

 

 

 

H

L

H

Dout(n+1)

 

Increment

Counter Enabled—Internal Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Generation

Notes

34.“X” = “Don’t Care”, “H” = VIH, “L” = VIL.

35.ADS, CNTEN, CNTRST = “Don’t Care.”

36.OE is an asynchronous input signal.

37.When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle.

38.CE0 and OE = VIL; CE1 and R/W = VIH.

39.Data shown for flow-through mode; pipelined mode output will be delayed by one cycle.

40.Counter operation is independent of CE0 and CE1.

Document #: 38-06043 Rev. *C

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesLogic Block Diagram Functional Description Pin ConfigurationsO2R VCC O3R O4R O5R O6R O7R O8R Pin Definitions Selection GuideDescription CY7C09079V/89V/99V CY7C09179V/89V/99VMaximum Ratings Electrical Characteristics Over the Operating RangeOperating Range CapacitanceALL Inputpulses Used for t CKLZ, t OLZ, & t OHZLoad 1 -6 and -7 only OutputPort to Port Delays Switching Characteristics Over the Operating RangeADS CntenData OUT CLKAddress Dataout Switching WaveformsClkl ADDRESSB1Datainl Valid CLK R Addressl MatchAddress R Match Data Outr ValidCE1 CLK CE0Data Read no Operation Write ReadRead Write Pipelined Read-to-Write-to-Read OE Controlled19, 26, 27Read Write Operation Flow-Through Read-to-Write-to-Read OE = VIL17, 19, 26, 27Read ADSRead with Counter Counter Hold External Address Read Counter Hold External Read with Counter With AddressADS Cnten Address InternalData Data OUT Counter Write Read Reset Address Counter Reset Pipelined Outputs19, 26, 32Mode Operation Read/Write and Enable Operation34, 35 Inputs Outputs0 -I/O Operation Address Counter Control Operation 34, 38, 39 PreviousPackage Type Operating Range Ordering InformationSpeed ns Ordering Code 64K x9 3.3V Synchronous Dual-Port Sram Pin Thin Plastic Quad Flat Pack Tqfp A100 Package DiagramDocument Number Rev ECN No Orig. Description of Change Sales, Solutions, and Legal InformationDocument History

CY7C09089V, CY7C09189V, CY7C09179V, CY7C09079V, CY7C09199V specifications

Cypress Semiconductor has developed a series of high-performance static random-access memory (SRAM) chips, including the CY7C09099V, CY7C09199V, CY7C09079V, CY7C09179V, and CY7C09189V. These SRAM products are designed for a wide array of applications, ranging from telecommunications and networking to consumer electronics, due to their high speed, low latency, and reliable performance.

One of the most notable features of these CY7C series devices is their high-density configuration. These chips generally offer densities ranging from 256Kb to 16Mb, making them suitable for various applications requiring significant memory capacity without sacrificing speed. Additionally, they typically incorporate a low-power architecture, allowing for efficient energy consumption, which is crucial in battery-operated devices.

The CY7C09099V and CY7C09199V variants are particularly noted for their high-speed access times, achieving data rate performance levels that meet the stringent requirements of modern computing tasks. The read and write access times can vary from 10ns to 15ns, ensuring that these devices can handle fast data processing demands. Their robust performance is complemented by features such as a single supply voltage that simplifies circuit design while providing ease of integration into various systems.

One of the advanced technologies used in these SRAM devices is the asynchronous read and write operation. This technology allows the memory to provide quick data retrieval and storage without the need for complex timing sequences, enhancing overall system responsiveness. Moreover, the chips feature a common data input/output interface, which simplifies communication protocols and reduces design complexity.

Another essential characteristic of the CY7C series is their wide operating temperature range, making them suitable for industrial applications. The ability to operate in diverse environmental conditions increases their reliability across different sectors. Embedded parity checking within the memory architecture helps to detect and correct errors, further ensuring data integrity.

Overall, Cypress’s CY7C09099V, CY7C09199V, CY7C09079V, CY7C09179V, and CY7C09189V SRAM devices represent a significant advancement in memory technology. With a blend of high-speed performance, low power consumption, and robust reliability, they are designed to meet the evolving needs of modern electronic applications, providing designers with a reliable solution for high-performance memory requirements.
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