Cypress CY62167EV30 manual Switching Waveforms

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CY62167EV30 MoBL®

Switching Waveforms

Figure 5 shows address transition controlled read cycle waveforms.[19, 20]

Figure 5. Read Cycle No. 1

tRC

ADDRESS

tAA

tOHA

DATA OUT

PREVIOUS DATA VALID

DATA VALID

Figure 6 shows OE controlled read cycle waveforms.[20, 21]

 

 

Figure 6. Read Cycle No. 2

 

ADDRESS

 

 

CE1

tRC

 

 

tPD

 

 

CE2

 

tHZCE

 

 

 

tACE

 

BHE/BLE

 

 

 

tDBE

tHZBE

 

tLZBE

 

OE

 

 

 

tDOE

tHZOE

 

tLZOE

HIGH

DATA OUT

HIGH IMPEDANCE

IMPEDANCE

DATA VALID

 

 

 

 

tLZCE

ICC

VCC

tPU

SUPPLY

50%

50%

 

ISB

CURRENT

 

Notes

19.The device is continuously selected. OE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH.

20.WE is HIGH for read cycle.

21.Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH.

Document #: 38-05446 Rev. *E

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Contents Functional Description FeaturesLogic Block Diagram Cypress Semiconductor Corporation 198 Champion CourtMin Typ5 Max CY62167EV30LL Pin ConfigurationProduct Portfolio BLE BHEOperating Range Electrical CharacteristicsMaximum Ratings CapacitanceData Retention Characteristics Thermal ResistanceVfbga Tsop Read Cycle Switching CharacteristicsParameter Description Ns Industrial/Auto-A Unit Min BHESwitching Waveforms Shows WE controlled write cycle waveforms.18, 22 Data I/O Valid DataShows CE1 or CE2 controlled write cycle waveforms.18, 22 Inputs/Outputs Mode Power Truth TableCE1 CE2 BHE BLE Package Diagrams Ordering InformationBall Vfbga 6 x 8 x 1 mm Pin Tsop I 12 mm x 18.4 mm x 1.0 mm Document History REV ECN noOrig. Submission Change Date Description of Change Sales, Solutions, and Legal Information USB