CY62167EV30 MoBL®
Switching Characteristics
Over the Operating Range[14, 15]
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| Description | 45 ns | Unit | |
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| Min | Max | |||
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READ CYCLE |
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tRC |
| Read Cycle Time | 45 |
| ns | ||||||
tAA |
| Address to Data Valid |
| 45 | ns | ||||||
tOHA |
| Data Hold from Address Change | 10 |
| ns | ||||||
tACE |
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| 1 LOW and CE2 HIGH to Data Valid |
| 45 | ns | |||||
CE |
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tDOE |
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| LOW to Data Valid |
| 22 | ns | |||
OE |
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tLZOE |
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| LOW to LOW Z[16] | 5 |
| ns | |||
OE |
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tHZOE |
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| HIGH to High Z[16, 17] |
| 18 | ns | |||
OE |
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tLZCE |
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| 1 LOW and CE2 HIGH to Low Z[16] | 10 |
| ns | |||||
CE |
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tHZCE |
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| 1 HIGH and CE2 LOW to High Z[16, 17] |
| 18 | ns | |||||
CE |
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tPU |
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| 1 LOW and CE2 HIGH to Power Up | 0 |
| ns | |||||
CE |
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tPD |
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| 1 HIGH and CE2 LOW to Power Down |
| 45 | ns | |||||
CE |
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tDBE |
| BLE / BHE LOW to Data Valid |
| 45 | ns | ||||||
tLZBE |
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| LOW to Low Z[16] | 10 |
| ns |
BLE | BHE |
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tHZBE |
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| HIGH to HIGH Z[16, 17] |
| 18 | ns |
BLE | BHE |
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WRITE CYCLE[18] |
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tWC |
| Write Cycle Time | 45 |
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tSCE |
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| 1 LOW and CE2 HIGH to Write End | 35 |
| ns | |||||
CE |
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tAW |
| Address Setup to Write End | 35 |
| ns | ||||||
tHA |
| Address Hold from Write End | 0 |
| ns | ||||||
tSA |
| Address Setup to Write Start | 0 |
| ns | ||||||
tPWE |
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| Pulse Width | 35 |
| ns | |||
WE |
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tBW |
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| LOW to Write End | 35 |
| ns |
BLE | BHE |
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tSD |
| Data Setup to Write End | 25 |
| ns | ||||||
tHD |
| Data Hold from Write End | 0 |
| ns | ||||||
tHZWE |
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| LOW to |
| 18 | ns | |||
WE |
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tLZWE |
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| HIGH to | 10 |
| ns | |||
WE |
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Notes
14.Test conditions for all parameters other than
15.AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
16.At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
17.tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
18.The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
Document #: | Page 5 of 14 |
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