Texas Instruments TSB12LV26 manual Switching Characteristics for PCI Interface§

7.3Electrical Characteristics Over Recommended Operating Conditions (unless otherwise noted)

			OPERATION			TEST		MIN	MAX	UNIT
					CONDITIONS
		PCI		IOH = ± 0.5 mA				0.9 VCC
				IOH = ± 2 mA				2.4
VOH	High-level output voltage	PHY interface		IOH = ± 4 ∝A				2.8		V
				IOH = ± 8 mA				VCC ± 0.6
		Miscellaneous³		IOH = ± 4 mA				VCC ± 0.6
		PCI		IOL = 1.5 mA					0.1 VCC
				IOL = 6 mA				0	0.55
VOL²	Low-level output voltage	PHY interface		IOL = 4 mA					0.4	V
				IOL = 8 mA
		Miscellaneous³		IOL = 4 mA					0.5
IOZ	3-state output high-impedance	Output pins	3.6 V	VO = VCC or GND					±20	∝A
		Input pins	3.6 V	V = GND³					±20
IIL	Low-level input current			I						∝A
		I/O pins²	3.6 V	V	= GND³			±20
				I
		PCI²	3.6 V	V = V		CC	³		±20
IIH	High-level input current			I						∝A
		Others²	3.6 V	V	= V	CC	³	±20
				I

²For I/O pins, input leakage (IIL and IIH) includes IOZ of the disabled output. ³ Miscellaneous pins are: GPIO2, GPIO3, SDA, SCL, CYCLEOUT.

7.4 Switching Characteristics for PCI Interface§

	PARAMETER	MEASURED	MIN	TYP MAX	UNIT
tsu	Setup time before PCLK	±50% to 50%	3		ns
th	Hold time before PCLK	±50% to 50%	0		ns
td	Delay time, PHY_CLK to data valid	±50% to 50%	2	6	ns

§These parameters are ensured by design.

7.5 Switching Characteristics for PHY-Link Interface§

	PARAMETER	MEASURED	MIN	TYP MAX	UNIT
tsu	Setup time, Dn, CTLn, LREQ to PHY_CLK	±50% to 50%	6		ns
th	Hold time, Dn, CTLn, LREQ before PHY_CLK	±50% to 50%	1		ns
td	Delay time, PHY_CLK to Dn, CTLn	±50% to 50%	2	11	ns

§These parameters are ensured by design.

7±3