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Texas Instruments TSB12LV26 manual

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Contents

Main Page Page Page Contents Section Title Page Page Page Page List of Tables Table Title Page Page 1 Introduction 1.1 Description PCI Bus Power Management Interface Specification 1394 Open Host Controller Interface Specification 1.3 Related Documents 1.4 Ordering Information 2 Terminal Descriptions Figure 21. Terminal Assignments Table 21. Signals Sorted by Terminal Number Table 22. Signal Names Sorted Alphanumerically to Terminal Number PCI Local Bus Specification Table 24. PCI System Terminals Table 25. PCI Address and Data Terminals Table 26. PCI Interface Control Terminals Table 27. IEEE 1394 PHY/Link Terminals Table 28. Miscellaneous Terminals Page 3 TSB12LV26 Controller Programming Model type Figure 31. TSB12LV26 Block Diagram 32 3.1 PCI Configuration Registers PCI Local Bus Specification 3.2 Vendor ID Register 3.3 Device ID Register 3.4 Command Register PCI Local Bus Specification 3.5 Status Register PCI Local Bus Specification 3.6 Class Code and Revision ID Register 3.7 Latency Timer and Class Cache Line Size Register 3.8 Header Type and BIST Register 3.9 OHCI Base Address Register 3.10 TI Extension Base Address Register OHCI Base Address Register 3.11 Subsystem Identification Register 3.12 Power Management Capabilities Pointer Register 3.13 Interrupt Line and Pin Register 3.14 MIN_GNT and MAX_LAT Register 3.15 OHCI Control Register 3.16 Capability ID and Next Item Pointer Register 3.17 Power Management Capabilities Register PCI Bus Power Management Interface Specification Rev. 1.0 3.18 Power Management Control and Status Register 3.19 Power Management Extension Register 3.20 Miscellaneous Configuration Register Register: Miscellaneous configuration Offset: F0h Default: 0000 2400h Table 317. Miscellaneous Configuration Register 3.21 Link Enhancement Control Register Register: Link enhancement control Offset: F4h Default: 0000 1000h Table 318. Link Enhancement Control Register Description 3.22 Subsystem Access Register 3.23 GPIO Control Register Page 4 OHCI Registers 1394 Open Host Controller Interface Specification Page Table 41. OHCI Register Map (Continued) 4.1 OHCI Version Register 4.2 GUID ROM Register 4.3 Asynchronous Transmit Retries Register 4.4 CSR Data Register 4.5 CSR Compare Register 4.6 CSR Control Register 4.7 Configuration ROM Header Register 4.8 Bus Identification Register 4.9 Bus Options Register Register: Bus options Offset: 20h Default: X0XX A0X2h Table 47. Bus Options Register Description 4.10 GUID High Register 4.11 GUID Low Register 4.12 Configuration ROM Mapping Register 4.13 Posted Write Address Low Register 4.14 Posted Write Address High Register 4.15 Vendor ID Register 4.16 Host Controller Control Register 4.17 Self-ID Buffer Pointer Register 4.18 Self-ID Count Register 4.19 Isochronous Receive Channel Mask High Register 4.20 Isochronous Receive Channel Mask Low Register 4.21 Interrupt Event Register Table 414. Interrupt Event Register Description (Continued) 4.22 Interrupt Mask Register 4.23 Isochronous Transmit Interrupt Event Register 4.24 Isochronous Transmit Interrupt Mask Register 4.25 Isochronous Receive Interrupt Event Register 4.26 Isochronous Receive Interrupt Mask Register 4.27 Fairness Control Register 4.28 Link Control Register 4.29 Node Identification Register 4.30 PHY Layer Control Register 4.31 Isochronous Cycle Timer Register 4.32 Asynchronous Request Filter High Register Table 423. Asynchronous Request Filter High Register Description (Continued) 4.33 Asynchronous Request Filter Low Register 4.34 Physical Request Filter High Register Table 425. Physical Request Filter High Register Description (Continued) 4.35 Physical Request Filter Low Register 4.36 Physical Upper Bound Register (Optional Register) 4.37 Asynchronous Context Control Register 4.38 Asynchronous Context Command Pointer Register 4.39 Isochronous Transmit Context Control Register 1394 Open Host Controller Interface Specification. 4.40 Isochronous Transmit Context Command Pointer Register 4.41 Isochronous Receive Context Control Register Table 430. Isochronous Receive Context Control Register Description (Continued) 4.42 Isochronous Receive Context Command Pointer Register 4.43 Isochronous Receive Context Match Register Page 5 GPIO Interface Page 6 Serial ROM Interface Table 62. Serial ROM Map 7 Electrical Characteristics 7.1 Absolute Maximum Ratings Over Operating Temperature Ranges 7.2 Recommended Operating Conditions 7.3 Electrical Characteristics Over Recommended Operating Conditions (unless otherwise noted) 7.4 Switching Characteristics for PCI Interface 7.5 Switching Characteristics for PHY-Link Interface Page 8 Mechanical Information PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK