Texas Instruments TSB12LV26 ±4. PCI System Terminals, PCIRST, terminal, Pciclk, As open-drain

			Table 2±4. PCI System Terminals
TERMINAL		I/O		DESCRIPTION
NAME	NO.
			Global power reset. This reset brings all of the TSB12LV26 internal registers to their default states, including
			those registers not reset by PCI_RST. When G_RST is asserted, the device is completely nonfunctional.
			When implementing wake capabilities from the 1394 host controller, it is necessary to implement two resets
G_RST	10	I
			to the TSB12LV26. G_RST should be a one-time power-on reset, and PCI_RST should be connected to the
			PCI bus RST. If wake capabilities are not required, G_RST may be connected to the PCI bus RST (see
			PCI_RST, terminal 76).
PCI_CLK	12	I	PCI bus clock. Provides timing for all transactions on the PCI bus. All PCI signals are sampled at rising edge
			of PCI_CLK.
			Interrupt signal. This output indicates interrupts from the TSB12LV26 to the host. This terminal is implemented
PCI_INTA	8	O
			as open-drain.
			PCI reset. When this bus reset is asserted, the TSB12LV26 places all output buffers in a high impedance state
			and resets all internal registers except device power management context- and vendor-specific bits initialized
			by host power-on software. When PCI_RST is asserted, the device is completely nonfunctional.
PCI_RST	76	I
			If this terminal is implemented, then it should be connected to the PCI bus RST signal. Otherwise, it should
			be pulled high to link VCC through a 4.7-kΩresistor, or strapped to the G_RST terminal (see G_RST, terminal
			10).

2±4