PZ Package TOP View, Vccp, Ccp | Texas Instruments TSB12LV26

2 Terminal Descriptions

This section provides the terminal descriptions for the TSB12LV26. Figure 2±1 shows the signal assigned to each terminal in the package. Table 2±1 is a listing of signal names arranged in terminal number order, and Table 2±2 lists terminals in alphanumeric order by signal names.

PZ PACKAGE

(TOP VIEW)

GND

GPIO2

GPIO3

SCL

SDA

VCCP

PCI_CLKRUN PCI_INTA 3.3 VCC

G_RST

GND PCI_CLK

3.3 VCC

PCI_GNT

PCI_REQ

VCCP

PCI_PME PCI_AD31 PCI_AD30 3.3 VCC PCI_AD29 PCI_AD28 PCI_AD27

GND PCI_AD26

		REG18		LPSPHY		LINKONPHY		LREQPHY		V3.3		SCLKPHY		GND		CTL0PHY			CTL1PHY		V3.3		DATA0PHY		DATA1PHY		DATA2PHY		V		DATA3PHY		DATA4PHY			DATA5PHY			GND		DATA6PHY		DATA7PHY		V3.3		ENREG		CYCLEIN		CYCLEOUT		RSTPCI
										CC											CC								CCP																CC
																													CCP



	100			99		98		97		96		95		94		93		92			91		90		89		88		87		86		85			84			83		82		81		80		79		78		77		76
	1																																																				75
	2																																																				74
	2																																																				74
	3																																																				73
	3																																																				73
	4																																																				72
	4																																																				72
	5																																																				71
	5																																																				71
	6																																																				70
	6																																																				70
	7																																																				69
	7																																																				69
	8																																																				68
	8																																																				68
	9																																																				67
	9																																																				67
	10																																																				66
	10																																																				66
	11																																																				65
	11																																																				65
	12																																																				64
	12																																																				64
	13																																																				63
	13																																																				63
	14																																																				62
	14																																																				62
	15																																																				61
	15																																																				61
	16																																																				60
	16																																																				60
	17																																																				59
	17																																																				59
	18																																																				58
	18																																																				58
	19																																																				57
	19																																																				57
	20																																																				56
	20																																																				56
	21																																																				55
	21																																																				55
	22																																																				54
	22																																																				54
	23																																																				53
	23																																																				53
	24																																																				52
	24																																																				52
	25																										38				40					42					44										49		51
	25																																																				51
	26			27		28		29		30		31		32		33		34			35		36		37				39				41						43				45		46		47		48				50


		PCIAD25		PCIAD24		PCIC/BE3		PCIIDSEL		GND		PCIAD23		PCIAD22		PCIAD21		PCIAD20			3.3V		PCIAD19		PCIAD18		PCIAD17		V		PCIAD16			C/BE2PCI			REG18		FRAMEPCI		PCIIRDY		PCITRDY		3.3V		DEVSELPCI		PCISTOP		PCIPERR		GND
																					CC								CCP																CC

GND PCI_AD0

PCI_AD1 PCI_AD2

PCI_AD3

3.3VCC

PCI_AD4

PCI_AD5 PCI_AD6 PCI_AD7

PCI_C/BE0 PCI_AD8

VCCP

PCI_AD9 PCI_AD10

GND

PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14

3.3VCC

PCI_AD15 PCI_C/BE1

PCI_PAR PCI_SERR

Figure 2±1. Terminal Assignments

2±1

Image 13

Texas Instruments TSB12LV26 manual PZ Package TOP View, Vccp Pciclkrun Pciinta 3.3 VCC, Ccp, Pciirdy

TSB12LV26 specifications

The Texas Instruments TSB12LV26 is a high-performance, low-voltage transceiver designed for Serial Bus applications. It is widely recognized for its robust features and versatility, making it a popular choice among engineers and designers in various industries. One of the primary features of the TSB12LV26 is its support for high-speed data transmission, enabling it to operate at speeds up to 400 Mbps. This capability is essential for applications that demand rapid data transfer, such as in multimedia and communication systems.

The TSB12LV26 is part of the IEEE 1394 standard, also known as FireWire, which is widely used for connecting devices like digital cameras, external hard drives, and printers. The chip operates within a voltage range of 2.7V to 3.6V, making it suitable for low-power applications where energy efficiency is critical. The integration of advanced Low-Voltage Differential Signaling (LVDS) technology within the TSB12LV26 enhances signal integrity and reduces electromagnetic interference, resulting in more reliable performance over longer distances.

In terms of its physical characteristics, the TSB12LV26 is available in a compact 48-pin HTQFP package, which is beneficial for space-constrained designs. The device features a comprehensive set of input and output pins, allowing for flexible connectivity options. Additionally, the TSB12LV26 includes advanced power management features, including low-power modes that help extend battery life in portable devices.

Another significant advantage of the TSB12LV26 is its capability for peer-to-peer communication, enabling devices to connect and communicate directly without the need for a central controller. This functionality supports a wide range of device configurations and simplifies system architecture. Furthermore, the transceiver offers built-in support for asynchronous and isochronous data transfer, making it adaptable for various application requirements.

The TSB12LV26 also adheres to stringent EMI and ESD protection standards, ensuring reliable operation in challenging environments. With a rich feature set, excellent performance characteristics, and compliance with industry standards, the Texas Instruments TSB12LV26 remains an ideal choice for engineers looking to implement high-speed and reliable communication in their designs. Overall, it represents a significant advancement in the field of data transmission technology, making it a preferred component for numerous electronic applications.

Contents

Data Manual SLLS366A TSB12LV26 Important Notice Contents Page Mechanical Information List of Illustrations Vii List of Tables Viii Description Features Ordering Information Related DocumentsOrdering Number Name Voltage Package OHCI-Lynx PCI-Based Ieee 1394 Host Controller Vccp Pciclkrun Pciinta 3.3 VCC PZ Package TOP ViewVccp CCP Terminal Name ±1. Signals Sorted by Terminal Number ±3. Power Supply Terminals ±2. Signal Names Sorted Alphanumerically to Terminal NumberTerminal Description Name PCIRST, terminal ±4. PCI System TerminalsPciclk As open-drain ±5. PCI Address and Data Terminals During the data phase, AD31±AD0 contain data Pcic BE0 ±6. PCI Interface Control TerminalsIrdy Pcitrdy ±8. Miscellaneous Terminals ±7. Ieee 1394 PHY/Link TerminalsPage Access TAG Name Meaning ±1. Bit Field Access Tag Descriptions ±1. TSB12LV26 Block Diagram ±2. PCI Configuration Register Map PCI Configuration RegistersVendor ID Register Register Name Offset Command Command Register±3. Command Register Description Device ID Register Status Status Register±4. Status Register Description Latency timer and class cache line size Latency Timer and Class Cache Line Size RegisterClass Code and Revision ID Register Class code and revision ID Ohci Base Address Register Header Type and Bist Register Subsystem Identification Register TI Extension Base Address RegisterTI extension base address Subsystem identification Register Power management capabilities pointer Power Management Capabilities Pointer RegisterInterrupt Line and Pin Register Register Interrupt line and pin Ohci Control Register Mingnt and Maxlat Register Register Capability ID and next item pointer Capability ID and Next Item Pointer RegisterNextitem Capabilityid Register Power management capabilities Power Management Capabilities Register±14. Power Management Capabilities Register Description Power Management Extension Register Power Management Control and Status RegisterPower management control and status Power management extension Miscellaneous configuration Miscellaneous Configuration Register±17. Miscellaneous Configuration Register Link enhancement control Link Enhancement Control Register±18. Link Enhancement Control Register Description Subsystem access Subsystem Access Register±19. Subsystem Access Register Description Subdevid Gpio control Gpio Control Register±20. Gpio Control Register Description ±18 DMA Context Register Name Abbreviation Offset ±1. Ohci Register MapGuid ROM Guidrom Isochronous receive interrupt mask IsoRecvIntMaskSet IsoRecvIntEventClearPhysicalRequestFilterHiClear Physical request filter low PhysicalRequestFilterLoSet Isochronous receive context command Isochronous transmit context commandCommandPtr 40Ch + 32*n Pointer Context match ContextMatch Asynchronous context control ContextControlSet Ohci version Ohci Version Register±2. Ohci Version Register Description ±3. Guid ROM Register Description Guid ROM RegisterGuid ROM RSU CSR Data Register Asynchronous Transmit Retries RegisterAsynchronous transmit retries ±4. Asynchronous Transmit Retries Register Description CSR Control Register CSR Compare RegisterCSR compare CSR control Configuration ROM header Configuration ROM Header Register±6. Configuration ROM Header Register Description Bus Identification Register Bus options Bus Options Register±7. Bus Options Register Description Guid Low Register Guid High RegisterGuid high Guid low Configuration ROM mapping Configuration ROM Mapping Register±8. Configuration ROM Mapping Register Description Posted Write Address Low Register Posted write address high Posted Write Address High Register±9. Posted Write Address High Register Description Vendor ID Host controller control Host Controller Control Register±10. Host Controller Control Register Description Self-ID Count Register Self-ID Buffer Pointer RegisterSelf ID-buffer pointer Self-ID count Isochronous receive channel mask high Isochronous Receive Channel Mask High Register Isochronous receive channel mask low Isochronous Receive Channel Mask Low Register Interrupt event Interrupt Event Register±14. Interrupt Event Register Description Arrq Rscu Arrs Rscu Interrupt mask Interrupt Mask Register±15. Interrupt Mask Register Description Rscu RSC Isochronous transmit interrupt event Isochronous Transmit Interrupt Event Register Isochronous transmit interrupt mask Isochronous Transmit Interrupt Mask Register±21 Isochronous transmit interrupt mask Isochronous Receive Interrupt Mask Register Isochronous Receive Interrupt Event RegisterIsochronous receive interrupt event Isochronous receive interrupt mask Fairness control Fairness Control Register±18. Fairness Control Register Description Fairness control Link control Link Control Register±19. Link Control Register Description Node identification Node Identification Register±20. Node Identification Register Description CPS PHY layer control PHY Layer Control Register±21. PHY Control Register Description Isochronous cycle timer Isochronous Cycle Timer Register±22. Isochronous Cycle Timer Register Description 24±12 Asynchronous request filter high Asynchronous Request Filter High Register±23. Asynchronous Request Filter High Register Description ±29 Asynchronous request filter low Asynchronous Request Filter Low Register±24. Asynchronous Request Filter Low Register Description ±30 Physical request filter high Physical Request Filter High Register±25. Physical Request Filter High Register Description Are accepted ±32 Physical request filter low Physical Request Filter Low Register±26. Physical Request Filter Low Register Description Physical request filter low Physical upper bound Physical Upper Bound Register Optional RegisterPhysical upper bound ±34 Asynchronous context control Asynchronous Context Control Register±27. Asynchronous Context Control Register Description Rscu RSU Asynchronous context command pointer Asynchronous Context Command Pointer Register31±4 DescriptorAddress Isochronous transmit context control Isochronous Transmit Context Control RegisterRSC RSU Isochronous transmit context command pointer Isochronous Transmit Context Command Pointer RegisterIsochronous Receive Context Control Register Isochronous receive context control Reserved. Bits 27±16 return 0s when read CycleMatchEnableMultiChanMode Match register see .43 is ignored Isochronous receive context command pointer Isochronous Receive Context Command Pointer RegisterIsochronous receive context command pointer ±40 Isochronous Receive Context Match Register When the command descriptor w field is set to 11bIsochronous receive context match ±31. Isochronous Receive Context Match Register Description ±42 Gpio Interface Page ROM Offset OHCI/PCI Offset Register Bits Loaded From ROM ±1. Registers and Bits Loadable through Serial ROM13h PCI register 40h PCI Ohci register Byte Byte Description Address ±2. Serial ROM MapRsvd PME Absolute Maximum Ratings Over Operating Temperature Ranges² Electrical Characteristics Operation MIN NOM Recommended Operating ConditionsUnit Switching Characteristics for PHY-Link Interface§ Switching Characteristics for PCI Interface§Operation Test MIN MAX Unit Conditions Parameter Measured MIN TYP MAX UnitPage PZ S-PQFP-G100 Mechanical InformationPage Important Notice