Manuals / Texas Instruments / Computer Equipment / Network Card

Texas Instruments TSB12LV26 manual ±1. Signals Sorted by Terminal Number, Terminal Name

Models: TSB12LV26

1 91

Download 91 pages 7.41 Kb

Page 14

Table 2±1. Signals Sorted by Terminal Number

NO.	TERMINAL NAME										NO.	TERMINAL NAME												NO.	TERMINAL NAME					NO.	TERMINAL NAME

1				GND							26					PCI_AD25								51						76
1				GND							26					PCI_AD25								51		PCI_SERR				76		PCI_RST

2				GPIO2							27					PCI_AD24								52		PCI_PAR				77	CYCLEOUT

3				GPIO3							28													53						78	CYCLEIN
3				GPIO3							28			PCI_C/BE3										53	PCI_C/BE1					78	CYCLEIN

4				SCL							29			PCI_IDSEL										54		PCI_AD15				79
4				SCL							29			PCI_IDSEL										54		PCI_AD15				79		REG_EN

5				SDA							30					GND								55		3.3 VCC				80		3.3 VCC
6				VCCP							31					PCI_AD23								56		PCI_AD14				81	PHY_DATA7
7											32					PCI_AD22								57		PCI_AD13				82	PHY_DATA6
7		PCI_CLKRUN									32					PCI_AD22								57		PCI_AD13				82	PHY_DATA6

8											33					PCI_AD21								58		PCI_AD12				83		GND
8			PCI_INTA								33					PCI_AD21								58		PCI_AD12				83		GND

9			3.3 VCC								34					PCI_AD20								59		PCI_AD11				84	PHY_DATA5
10											35					3.3 VCC								60		GND				85	PHY_DATA4
10				G_RST							35					3.3 VCC								60		GND				85	PHY_DATA4
11				GND							36					PCI_AD19								61		PCI_AD10				86	PHY_DATA3

12			PCI_CLK								37					PCI_AD18								62		PCI_AD9				87		VCCP
13			3.3 VCC								38					PCI_AD17								63		VCCP				88	PHY_DATA2
14											39					VCCP								64		PCI_AD8				89	PHY_DATA1
14			PCI_GNT								39					VCCP								64		PCI_AD8				89	PHY_DATA1
15											40					PCI_AD16								65						90	PHY_DATA0
15			PCI_REQ								40					PCI_AD16								65	PCI_C/BE0					90	PHY_DATA0

16				VCCP							41
16				VCCP							41			PCI_C/BE2										66		PCI_AD7				91		3.3 VCC
17											42					REG18								67		PCI_AD6				92	PHY_CTL1
17			PCI_PME								42					REG18								67		PCI_AD6				92	PHY_CTL1

18		PCI_AD31									43													68		PCI_AD5				93	PHY_CTL0
18		PCI_AD31									43			PCI_FRAME										68		PCI_AD5				93	PHY_CTL0

19		PCI_AD30									44													69		PCI_AD4				94		GND
19		PCI_AD30									44					PCI_IRDY								69		PCI_AD4				94		GND

20			3.3 VCC								45													70		3.3 VCC				95	PHY_SCLK
20			3.3 VCC								45				PCI_TRDY									70		3.3 VCC				95	PHY_SCLK
21		PCI_AD29									46					3.3 VCC								71		PCI_AD3				96		3.3 VCC
22		PCI_AD28									47													72		PCI_AD2				97	PHY_LREQ
22		PCI_AD28									47		PCI_DEVSEL											72		PCI_AD2				97	PHY_LREQ

23		PCI_AD27									48													73		PCI_AD1				98	PHY_LINKON
23		PCI_AD27									48					PCI_STOP								73		PCI_AD1				98	PHY_LINKON

24				GND							49													74		PCI_AD0				99	PHY_LPS
24				GND							49				PCI_PERR									74		PCI_AD0				99	PHY_LPS

25		PCI_AD26									50					GND								75		GND				100		REG18

2±2

Image 14

Texas Instruments TSB12LV26 manual ±1. Signals Sorted by Terminal Number, Terminal Name

TSB12LV26 specifications

The Texas Instruments TSB12LV26 is a high-performance, low-voltage transceiver designed for Serial Bus applications. It is widely recognized for its robust features and versatility, making it a popular choice among engineers and designers in various industries. One of the primary features of the TSB12LV26 is its support for high-speed data transmission, enabling it to operate at speeds up to 400 Mbps. This capability is essential for applications that demand rapid data transfer, such as in multimedia and communication systems.

The TSB12LV26 is part of the IEEE 1394 standard, also known as FireWire, which is widely used for connecting devices like digital cameras, external hard drives, and printers. The chip operates within a voltage range of 2.7V to 3.6V, making it suitable for low-power applications where energy efficiency is critical. The integration of advanced Low-Voltage Differential Signaling (LVDS) technology within the TSB12LV26 enhances signal integrity and reduces electromagnetic interference, resulting in more reliable performance over longer distances.

In terms of its physical characteristics, the TSB12LV26 is available in a compact 48-pin HTQFP package, which is beneficial for space-constrained designs. The device features a comprehensive set of input and output pins, allowing for flexible connectivity options. Additionally, the TSB12LV26 includes advanced power management features, including low-power modes that help extend battery life in portable devices.

Another significant advantage of the TSB12LV26 is its capability for peer-to-peer communication, enabling devices to connect and communicate directly without the need for a central controller. This functionality supports a wide range of device configurations and simplifies system architecture. Furthermore, the transceiver offers built-in support for asynchronous and isochronous data transfer, making it adaptable for various application requirements.

The TSB12LV26 also adheres to stringent EMI and ESD protection standards, ensuring reliable operation in challenging environments. With a rich feature set, excellent performance characteristics, and compliance with industry standards, the Texas Instruments TSB12LV26 remains an ideal choice for engineers looking to implement high-speed and reliable communication in their designs. Overall, it represents a significant advancement in the field of data transmission technology, making it a preferred component for numerous electronic applications.

Contents

Data Manual SLLS366A TSB12LV26 Important Notice Contents Page Mechanical Information List of Illustrations List of Tables Vii Viii Features Description Ordering Number Name Voltage Package Related DocumentsOrdering Information OHCI-Lynx PCI-Based Ieee 1394 Host Controller Vccp PZ Package TOP ViewVccp Pciclkrun Pciinta 3.3 VCC CCP ±1. Signals Sorted by Terminal Number Terminal Name Terminal Description Name ±2. Signal Names Sorted Alphanumerically to Terminal Number±3. Power Supply Terminals Pciclk ±4. PCI System TerminalsPCIRST, terminal As open-drain During the data phase, AD31±AD0 contain data ±5. PCI Address and Data Terminals Irdy ±6. PCI Interface Control TerminalsPcic BE0 Pcitrdy ±7. Ieee 1394 PHY/Link Terminals ±8. Miscellaneous TerminalsPage ±1. Bit Field Access Tag Descriptions Access TAG Name Meaning ±1. TSB12LV26 Block Diagram Vendor ID Register PCI Configuration Registers±2. PCI Configuration Register Map Register Name Offset ±3. Command Register Description Command RegisterCommand Device ID Register ±4. Status Register Description Status RegisterStatus Class Code and Revision ID Register Latency Timer and Class Cache Line Size RegisterLatency timer and class cache line size Class code and revision ID Header Type and Bist Register Ohci Base Address Register TI extension base address TI Extension Base Address RegisterSubsystem Identification Register Subsystem identification Interrupt Line and Pin Register Power Management Capabilities Pointer RegisterRegister Power management capabilities pointer Register Interrupt line and pin Mingnt and Maxlat Register Ohci Control Register Nextitem Capability ID and Next Item Pointer RegisterRegister Capability ID and next item pointer Capabilityid ±14. Power Management Capabilities Register Description Power Management Capabilities RegisterRegister Power management capabilities Power management control and status Power Management Control and Status RegisterPower Management Extension Register Power management extension ±17. Miscellaneous Configuration Register Miscellaneous Configuration RegisterMiscellaneous configuration ±18. Link Enhancement Control Register Description Link Enhancement Control RegisterLink enhancement control ±19. Subsystem Access Register Description Subsystem Access RegisterSubsystem access Subdevid ±20. Gpio Control Register Description Gpio Control RegisterGpio control ±18 Guid ROM Guidrom ±1. Ohci Register MapDMA Context Register Name Abbreviation Offset PhysicalRequestFilterHiClear IsoRecvIntEventClearIsochronous receive interrupt mask IsoRecvIntMaskSet Physical request filter low PhysicalRequestFilterLoSet CommandPtr 40Ch + 32*n Pointer Context match ContextMatch Isochronous transmit context commandIsochronous receive context command Asynchronous context control ContextControlSet ±2. Ohci Version Register Description Ohci Version RegisterOhci version Guid ROM Guid ROM Register±3. Guid ROM Register Description RSU Asynchronous transmit retries Asynchronous Transmit Retries RegisterCSR Data Register ±4. Asynchronous Transmit Retries Register Description CSR compare CSR Compare RegisterCSR Control Register CSR control ±6. Configuration ROM Header Register Description Configuration ROM Header RegisterConfiguration ROM header Bus Identification Register ±7. Bus Options Register Description Bus Options RegisterBus options Guid high Guid High RegisterGuid Low Register Guid low ±8. Configuration ROM Mapping Register Description Configuration ROM Mapping RegisterConfiguration ROM mapping Posted Write Address Low Register ±9. Posted Write Address High Register Description Posted Write Address High RegisterPosted write address high Vendor ID ±10. Host Controller Control Register Description Host Controller Control RegisterHost controller control Self ID-buffer pointer Self-ID Buffer Pointer RegisterSelf-ID Count Register Self-ID count Isochronous Receive Channel Mask High Register Isochronous receive channel mask high Isochronous Receive Channel Mask Low Register Isochronous receive channel mask low ±14. Interrupt Event Register Description Interrupt Event RegisterInterrupt event Arrs Rscu Arrq Rscu ±15. Interrupt Mask Register Description Interrupt Mask RegisterInterrupt mask Rscu RSC Isochronous Transmit Interrupt Event Register Isochronous transmit interrupt event ±21 Isochronous Transmit Interrupt Mask RegisterIsochronous transmit interrupt mask Isochronous transmit interrupt mask Isochronous receive interrupt event Isochronous Receive Interrupt Event RegisterIsochronous Receive Interrupt Mask Register Isochronous receive interrupt mask ±18. Fairness Control Register Description Fairness Control RegisterFairness control Fairness control ±19. Link Control Register Description Link Control RegisterLink control ±20. Node Identification Register Description Node Identification RegisterNode identification CPS ±21. PHY Control Register Description PHY Layer Control RegisterPHY layer control ±22. Isochronous Cycle Timer Register Description Isochronous Cycle Timer RegisterIsochronous cycle timer 24±12 ±23. Asynchronous Request Filter High Register Description Asynchronous Request Filter High RegisterAsynchronous request filter high ±29 ±24. Asynchronous Request Filter Low Register Description Asynchronous Request Filter Low RegisterAsynchronous request filter low ±30 ±25. Physical Request Filter High Register Description Physical Request Filter High RegisterPhysical request filter high Are accepted ±32 ±26. Physical Request Filter Low Register Description Physical Request Filter Low RegisterPhysical request filter low Physical request filter low Physical upper bound Physical Upper Bound Register Optional RegisterPhysical upper bound ±34 ±27. Asynchronous Context Control Register Description Asynchronous Context Control RegisterAsynchronous context control Rscu RSU 31±4 DescriptorAddress Asynchronous Context Command Pointer RegisterAsynchronous context command pointer RSC RSU Isochronous Transmit Context Control RegisterIsochronous transmit context control Isochronous Receive Context Control Register Isochronous Transmit Context Command Pointer RegisterIsochronous transmit context command pointer Isochronous receive context control MultiChanMode CycleMatchEnableReserved. Bits 27±16 return 0s when read Match register see .43 is ignored Isochronous receive context command pointer Isochronous Receive Context Command Pointer RegisterIsochronous receive context command pointer ±40 Isochronous receive context match When the command descriptor w field is set to 11bIsochronous Receive Context Match Register ±31. Isochronous Receive Context Match Register Description ±42 Gpio Interface Page 13h PCI register 40h PCI Ohci register ±1. Registers and Bits Loadable through Serial ROMROM Offset OHCI/PCI Offset Register Bits Loaded From ROM Rsvd PME ±2. Serial ROM MapByte Byte Description Address Electrical Characteristics Absolute Maximum Ratings Over Operating Temperature Ranges² Unit Recommended Operating ConditionsOperation MIN NOM Operation Test MIN MAX Unit Conditions Switching Characteristics for PCI Interface§Switching Characteristics for PHY-Link Interface§ Parameter Measured MIN TYP MAX UnitPage Mechanical Information PZ S-PQFP-G100Page Important Notice