Texas Instruments TSB12LV26 manual ±6. PCI Interface Control Terminals, Pcic BE0, Irdy, Pcitrdy

Table 2±6. PCI Interface Control Terminals

TERMINAL

I/O

DESCRIPTION

NAME

NO.

PCI_C/

65

BE0

PCI bus commands and byte enables. The command and byte enable signals are multiplexed on the same PCI

PCI_C/BE1

53

I/O

terminals. During the address phase of a bus cycle PCI_C/BE3±PCI_C/BE0 defines the bus command. During

PCI_C/BE2

41

the data phase, this 4-bit bus is used as byte enables.

PCI_C/BE3

28

Clock run. This terminal provides clock control through the

protocol. An internal pulldown

PCI_CLKRUN

PCI_CLKRUN

7

I/O

resistor is implemented on this terminal.

This terminal is implemented as open-drain.

PCI device select. The TSB12LV26 asserts this signal to claim a PCI cycle as the target device. As a PCI

PCI_DEVSEL

47

I/O

initiator, the TSB12LV26 monitors this signal until a target responds. If no target responds before time-out

occurs, then the TSB12LV26 terminates the cycle with an initiator abort.

PCI cycle frame. This signal is driven by the initiator of a PCI bus cycle.

is asserted to indicate

PCI_FRAME

PCI_FRAME

43

I/O

that a bus transaction is beginning, and data transfers continue while this signal is asserted. When PCI_FRAME

is deasserted, the PCI bus transaction is in the final data phase.

PCI bus grant. This signal is driven by the PCI bus arbiter to grant the TSB12LV26 access to the PCI bus after

PCI_GNT

14

I

the current data transaction has completed. This signal may or may not follow a PCI bus request, depending

upon the PCI bus parking algorithm.

PCI_IDSEL

29

I

Initialization device select. IDSEL selects the TSB12LV26 during configuration space accesses. IDSEL can be

connected to one of the upper 24 PCI address lines on the PCI bus.

PCI initiator ready.

indicates the ability of the PCI bus initiator to complete the current data phase of the

IRDY

PCI_IRDY

44

I/O

transaction. A data phase is completed upon a rising edge of PCLK where both PCI_IRDY and PCI_TRDY are

asserted.

PCI parity. In all PCI bus read and write cycles, the TSB12LV26 calculates even parity across the AD and C/BE

PCI_PAR

52

I/O

buses. As an initiator during PCI cycles, the TSB12LV26 outputs this parity indicator with a one PCI_CLK delay.

As a target during PCI cycles, the calculated parity is compared to the initiator parity indicator; a miscompare

can result in a parity error assertion (PCI_PERR).

PCI parity error indicator. This signal is driven by a PCI device to indicate that calculated parity does not match

PCI_PERR

49

I/O

PCI_PAR when PERR_ENB (bit 6) is set in the PCI command register (offset 04h, see Section 3.4).

17

O

Power management event. This terminal indicates wake events to the host.

PCI_PME

PCI bus request. Asserted by the TSB12LV26 to request access to the bus as an initiator. The host arbiter

PCI_REQ

15

O

asserts the PCI_GNT signal when the TSB12LV26 has been granted access to the bus.

PCI system error. When SERR_ENB (bit 8) in the PCI command register (offset 04h, see Section 3.4) is set

the output is pulsed, indicating an address parity error has occurred. The TSB12LV26 needs not be the target

PCI_SERR

51

O

of the PCI cycle to assert this signal.

This terminal is implemented as open-drain.

PCI cycle stop signal. This signal is driven by a PCI target to request the initiator to stop the current PCI bus

PCI_STOP

48

I/O

transaction. This signal is used for target disconnects, and is commonly asserted by target devices which do

not support burst data transfers.

PCI target ready.

indicates the ability of the PCI bus targer to complete the current data phase of

PCI_TRDY

PCI_TRDY

45

I/O

the transaction. A data phase is completed upon a rising edge of PCI_CLK where both PCI_IRDY and

PCI_TRDY are asserted.

2±6