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Texas Instruments TSB12LV26 manual Isochronous Transmit Interrupt Mask Register, ±21

Models: TSB12LV26

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4.24 Isochronous Transmit Interrupt Mask Register

The isochronous transmit interrupt mask set/clear register is used to enable the isochTx interrupt source on a per-channel basis. Reads from either the set register or the clear register always return the contents of the isochronous transmit interrupt mask register. In all cases the enables for each interrupt event align with the event register bits detailed in Table 4±16.

Bit	31	30	29	28	27	26		25	24	23	22	21	20	19	18	17	16

Name							Isochronous transmit interrupt mask

Type	R	R	R	R	R	R		R	R	R	R	R	R	R	R	R	R

Default	0	0	0	0	0	0	0		0	0	0	0	0	0	0	0	0

Bit

Name

Isochronous transmit interrupt mask

Type

RSC

Default

Isochronous transmit interrupt mask

Type:

Read/Set/Clear, Read-only

Offset:

98h

set register

9Ch

clear register

Default:

0000 00XXh

4±21

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Image 59

Texas Instruments TSB12LV26 manual Isochronous Transmit Interrupt Mask Register, Isochronous transmit interrupt mask, ±21

TSB12LV26 specifications

The Texas Instruments TSB12LV26 is a high-performance, low-voltage transceiver designed for Serial Bus applications. It is widely recognized for its robust features and versatility, making it a popular choice among engineers and designers in various industries. One of the primary features of the TSB12LV26 is its support for high-speed data transmission, enabling it to operate at speeds up to 400 Mbps. This capability is essential for applications that demand rapid data transfer, such as in multimedia and communication systems.

The TSB12LV26 is part of the IEEE 1394 standard, also known as FireWire, which is widely used for connecting devices like digital cameras, external hard drives, and printers. The chip operates within a voltage range of 2.7V to 3.6V, making it suitable for low-power applications where energy efficiency is critical. The integration of advanced Low-Voltage Differential Signaling (LVDS) technology within the TSB12LV26 enhances signal integrity and reduces electromagnetic interference, resulting in more reliable performance over longer distances.

In terms of its physical characteristics, the TSB12LV26 is available in a compact 48-pin HTQFP package, which is beneficial for space-constrained designs. The device features a comprehensive set of input and output pins, allowing for flexible connectivity options. Additionally, the TSB12LV26 includes advanced power management features, including low-power modes that help extend battery life in portable devices.

Another significant advantage of the TSB12LV26 is its capability for peer-to-peer communication, enabling devices to connect and communicate directly without the need for a central controller. This functionality supports a wide range of device configurations and simplifies system architecture. Furthermore, the transceiver offers built-in support for asynchronous and isochronous data transfer, making it adaptable for various application requirements.

The TSB12LV26 also adheres to stringent EMI and ESD protection standards, ensuring reliable operation in challenging environments. With a rich feature set, excellent performance characteristics, and compliance with industry standards, the Texas Instruments TSB12LV26 remains an ideal choice for engineers looking to implement high-speed and reliable communication in their designs. Overall, it represents a significant advancement in the field of data transmission technology, making it a preferred component for numerous electronic applications.

Contents

Data Manual SLLS366A TSB12LV26 Important Notice Contents Page Mechanical Information List of Illustrations Vii List of Tables Viii Description Features OHCI-Lynx PCI-Based Ieee 1394 Host Controller Related DocumentsOrdering Information Ordering Number Name Voltage Package CCP PZ Package TOP ViewVccp Pciclkrun Pciinta 3.3 VCC Vccp Terminal Name ±1. Signals Sorted by Terminal Number Terminal Description Name ±2. Signal Names Sorted Alphanumerically to Terminal Number±3. Power Supply Terminals As open-drain ±4. PCI System TerminalsPCIRST, terminal Pciclk ±5. PCI Address and Data Terminals During the data phase, AD31±AD0 contain data Pcitrdy ±6. PCI Interface Control TerminalsPcic BE0 Irdy ±8. Miscellaneous Terminals ±7. Ieee 1394 PHY/Link TerminalsPage Access TAG Name Meaning ±1. Bit Field Access Tag Descriptions ±1. TSB12LV26 Block Diagram Register Name Offset PCI Configuration Registers±2. PCI Configuration Register Map Vendor ID Register Device ID Register Command RegisterCommand ±3. Command Register Description ±4. Status Register Description Status RegisterStatus Class code and revision ID Latency Timer and Class Cache Line Size RegisterLatency timer and class cache line size Class Code and Revision ID Register Ohci Base Address Register Header Type and Bist Register Subsystem identification TI Extension Base Address RegisterSubsystem Identification Register TI extension base address Register Interrupt line and pin Power Management Capabilities Pointer RegisterRegister Power management capabilities pointer Interrupt Line and Pin Register Ohci Control Register Mingnt and Maxlat Register Capabilityid Capability ID and Next Item Pointer RegisterRegister Capability ID and next item pointer Nextitem ±14. Power Management Capabilities Register Description Power Management Capabilities RegisterRegister Power management capabilities Power management extension Power Management Control and Status RegisterPower Management Extension Register Power management control and status ±17. Miscellaneous Configuration Register Miscellaneous Configuration RegisterMiscellaneous configuration ±18. Link Enhancement Control Register Description Link Enhancement Control RegisterLink enhancement control Subdevid Subsystem Access RegisterSubsystem access ±19. Subsystem Access Register Description ±20. Gpio Control Register Description Gpio Control RegisterGpio control ±18 Guid ROM Guidrom ±1. Ohci Register MapDMA Context Register Name Abbreviation Offset Physical request filter low PhysicalRequestFilterLoSet IsoRecvIntEventClearIsochronous receive interrupt mask IsoRecvIntMaskSet PhysicalRequestFilterHiClear Asynchronous context control ContextControlSet Isochronous transmit context commandIsochronous receive context command CommandPtr 40Ch + 32*n Pointer Context match ContextMatch ±2. Ohci Version Register Description Ohci Version RegisterOhci version RSU Guid ROM Register±3. Guid ROM Register Description Guid ROM ±4. Asynchronous Transmit Retries Register Description Asynchronous Transmit Retries RegisterCSR Data Register Asynchronous transmit retries CSR control CSR Compare RegisterCSR Control Register CSR compare Bus Identification Register Configuration ROM Header RegisterConfiguration ROM header ±6. Configuration ROM Header Register Description ±7. Bus Options Register Description Bus Options RegisterBus options Guid low Guid High RegisterGuid Low Register Guid high Posted Write Address Low Register Configuration ROM Mapping RegisterConfiguration ROM mapping ±8. Configuration ROM Mapping Register Description Vendor ID Posted Write Address High RegisterPosted write address high ±9. Posted Write Address High Register Description ±10. Host Controller Control Register Description Host Controller Control RegisterHost controller control Self-ID count Self-ID Buffer Pointer RegisterSelf-ID Count Register Self ID-buffer pointer Isochronous receive channel mask high Isochronous Receive Channel Mask High Register Isochronous receive channel mask low Isochronous Receive Channel Mask Low Register ±14. Interrupt Event Register Description Interrupt Event RegisterInterrupt event Arrq Rscu Arrs Rscu Rscu RSC Interrupt Mask RegisterInterrupt mask ±15. Interrupt Mask Register Description Isochronous transmit interrupt event Isochronous Transmit Interrupt Event Register Isochronous transmit interrupt mask Isochronous Transmit Interrupt Mask RegisterIsochronous transmit interrupt mask ±21 Isochronous receive interrupt mask Isochronous Receive Interrupt Event RegisterIsochronous Receive Interrupt Mask Register Isochronous receive interrupt event Fairness control Fairness Control RegisterFairness control ±18. Fairness Control Register Description ±19. Link Control Register Description Link Control RegisterLink control CPS Node Identification RegisterNode identification ±20. Node Identification Register Description ±21. PHY Control Register Description PHY Layer Control RegisterPHY layer control 24±12 Isochronous Cycle Timer RegisterIsochronous cycle timer ±22. Isochronous Cycle Timer Register Description ±23. Asynchronous Request Filter High Register Description Asynchronous Request Filter High RegisterAsynchronous request filter high ±29 ±30 Asynchronous Request Filter Low RegisterAsynchronous request filter low ±24. Asynchronous Request Filter Low Register Description Are accepted Physical Request Filter High RegisterPhysical request filter high ±25. Physical Request Filter High Register Description ±32 Physical request filter low Physical Request Filter Low RegisterPhysical request filter low ±26. Physical Request Filter Low Register Description ±34 Physical Upper Bound Register Optional RegisterPhysical upper bound Physical upper bound Rscu RSU Asynchronous Context Control RegisterAsynchronous context control ±27. Asynchronous Context Control Register Description 31±4 DescriptorAddress Asynchronous Context Command Pointer RegisterAsynchronous context command pointer RSC RSU Isochronous Transmit Context Control RegisterIsochronous transmit context control Isochronous receive context control Isochronous Transmit Context Command Pointer RegisterIsochronous transmit context command pointer Isochronous Receive Context Control Register Match register see .43 is ignored CycleMatchEnableReserved. Bits 27±16 return 0s when read MultiChanMode ±40 Isochronous Receive Context Command Pointer RegisterIsochronous receive context command pointer Isochronous receive context command pointer ±31. Isochronous Receive Context Match Register Description When the command descriptor w field is set to 11bIsochronous Receive Context Match Register Isochronous receive context match ±42 Gpio Interface Page 13h PCI register 40h PCI Ohci register ±1. Registers and Bits Loadable through Serial ROMROM Offset OHCI/PCI Offset Register Bits Loaded From ROM Rsvd PME ±2. Serial ROM MapByte Byte Description Address Absolute Maximum Ratings Over Operating Temperature Ranges² Electrical Characteristics Unit Recommended Operating ConditionsOperation MIN NOM Parameter Measured MIN TYP MAX Unit Switching Characteristics for PCI Interface§Switching Characteristics for PHY-Link Interface§ Operation Test MIN MAX Unit ConditionsPage PZ S-PQFP-G100 Mechanical InformationPage Important Notice