Texas Instruments TSB12LV26 CycleMatchEnable, MultiChanMode, Match register see .43 is ignored

Table 4±30. Isochronous Receive Context Control Register Description (Continued)

BIT	FIELD NAME	TYPE	DESCRIPTION
			When this bit is set, the context begins running only when the 13-bit cycleMatch field (bits 24±12) in
			the isochronous receive context match register (see Section 4.43) matches the 13-bit cycleCount
29	cycleMatchEnable	RSCU	field in the cycleStart packet. The effects of this bit, however, are impacted by the values of other bits
			in this register. Once the context has become active, hardware clears this bit. The value of this bit
			must not be changed while bit 10 (active) or bit 15 (run) is set.
			When this bit is set, the corresponding isochronous receive DMA context receives packets for all
			isochronous channels enabled in the isochronous receive channel mask high (OHCI offset 70h/74h,
			see Section 4.19) and isochronous receive channel mask low (OHCI offset 78h/7Ch, see Section
			4.20) registers. The isochronous channel number specified in the isochronous receive context
28	multiChanMode	RSC	match register (see Section 4.43) is ignored.
			When this bit is cleared, the isochronous receive DMA context receives packets for that single
			channel. Only one isochronous receive DMA context may use the isochronous receive channel
			mask registers. If more than one isochronous receive context control register has this bit set, then
			results are undefined. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is
			set to 1.
27±16	RSVD	R	Reserved. Bits 27±16 return 0s when read.
15	run	RSCU	This bit is set by software to enable descriptor processing for the context and cleared by software to
			stop descriptor processing. The TSB12LV26 changes this bit only on a hardware or software reset.
14±13	RSVD	R	Reserved. Bits 14±13 return 0s when read.
12	wake	RSU	Software sets this bit to cause the TSB12LV26 to continue or resume descriptor processing. The
			TSB12LV26 clears this bit on every descriptor fetch.
11	dead	RU	The TSB12LV26 sets this bit when it encounters a fatal error and clears the bit when software resets
			bit 15 (run).
10	active	RU	The TSB12LV26 sets this bit to 1 when it is processing descriptors.
9±8	RSVD	R	Reserved. Bits 9±8 return 0s when read.
			This field indicates the speed at which the packet was received.
7±5	spd	RU	000 = 100 Mbits/sec,
			001 = 200 Mbits/sec, and
			010 = 400 Mbits/sec. All other values are reserved.
			For bufferFill mode, possible values are: ack_complete, evt_descriptor_read, evt_data_write, and
			evt_unknown. Packets with data errors (either dataLength mismatches or dataCRC errors) and
4±0	event code	RU	packets for which a FIFO overrun occurred are backed out. For packet-per-buffer mode, possible
			values are: ack_complete, ack_data_error, evt_long_packet, evt_overrun, evt_descriptor_read,
			evt_data_write, and evt_unknown.

4±39