Texas Instruments TSB12LV26 Device ID Register, Command Register, BIT Field Name Type Description

3.3 Device ID Register

The device ID register contains a value assigned to the TSB12LV26 by Texas Instruments. The device identification for the TSB12LV26 is 8020h.

Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Name								Device ID
Type	R	R	R	R	R	R	R	R	R	R	R	R	R	R	R	R
Default	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0

Register: Device ID

Type: Read-only

Offset: 02h

Default: 8020h

3.4 Command Register

The command register provides control over the TSB12LV26 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the bit descriptions of Table 3±3.

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Command

Type

R

R

R

R

R

R

R

R/W

R

R/W

R

R/W

R

R/W

R/W

R

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Register:

Command

Type:

Read/Write, Read-only

Offset:

04h

Default:

0000h

Table 3±3. Command Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

15±10

RSVD

R

Reserved. Bits 15±10 return 0s when read.

9

FBB_ENB

R

Fast back-to-back enable. The TSB12LV26 does not generate fast back-to-back transactions, thus

this bit returns 0 when read.

enable. When this bit is set, the TSB12LV26

driver is enabled.

can

8

SERR_ENB

R/W

PCI_SERR

PCI_SERR

PCI_SERR

be asserted after detecting an address parity error on the PCI bus.

7

STEP_ENB

R

Address/data stepping control. The TSB12LV26 does not support address/data stepping, thus this bit

is hardwired to 0.

Parity error enable. When this bit is set, the TSB12LV26 is enabled to drive

response to

6

PERR_ENB

R/W

PCI_PERR

parity errors through the PCI_PERR signal.

5

VGA_ENB

R

VGA palette snoop enable. The TSB12LV26 does not feature VGA palette snooping. This bit returns 0

when read.

Memory write and invalidate enable. When this bit is set, the TSB12LV26 is enabled to generate MWI

4

MWI_ENB

R/W

PCI bus commands. If this bit is cleared, then the TSB12LV26 generates memory write commands

instead.

3

SPECIAL

R

Special cycle enable. The TSB12LV26 function does not respond to special cycle transactions. This bit

returns 0 when read.

2

MASTER_ENB

R/W

Bus master enable. When this bit is set, the TSB12LV26 is enabled to initiate cycles on the PCI bus.

1

MEMORY_ENB

R/W

Memory response enable. Setting this bit enables the TSB12LV26 to respond to memory cycles on the

PCI bus. This bit must be set to access OHCI registers.

0

IO_ENB

R

I/O space enable. The TSB12LV26 does not implement any I/O mapped functionality; thus, this bit re-

turns 0 when read.

3±4