4.40 Isochronous Transmit Context Command Pointer Register

The isochronous transmit context command pointer register contains a pointer to the address of the first descriptor block that the TSB12LV26 accesses when software enables an isochronous transmit context by setting the isochronous transmit context control register (see Section 4.39) bit 15 (run). The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, … , 7).

Bit

31

 

30

29

28

 

27

26

25

24

23

22

 

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

Isochronous transmit context command pointer

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

R

R

 

R

R

R

R

R

R

 

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

X

 

X

X

X

 

X

X

X

X

X

X

 

X

X

X

X

X

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

15

 

14

13

12

 

11

10

9

8

7

6

 

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

Isochronous transmit context command pointer

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

R

R

 

R

R

R

R

R

R

 

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

X

 

X

X

X

 

X

X

X

X

X

X

 

X

X

X

X

X

X

 

Register:

Isochronous transmit context command pointer

 

 

 

 

 

 

 

Type:

 

Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

20Ch + (16 * n)

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

XXXX XXXXh

 

 

 

 

 

 

 

 

 

 

 

 

 

4.41 Isochronous Receive Context Control Register

The isochronous receive context control set/clear register controls options, state, and status for the isochronous receive DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3). See Table 4±30 for a complete description of the register contents.

Bit

 

31

 

30

 

29

 

28

 

27

26

25

 

24

23

 

22

 

21

20

 

19

 

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

 

Isochronous receive context control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

 

RSC

 

RSC

 

RSCU

 

RSC

 

R

R

R

 

R

R

 

R

 

R

R

 

R

 

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

 

X

 

X

 

 

X

 

X

 

0

0

0

 

0

0

 

0

 

0

0

 

0

 

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

 

15

 

14

 

13

 

12

 

11

10

9

 

8

7

 

6

 

5

4

 

3

 

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

 

Isochronous receive context control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

 

RSCU

 

R

 

 

R

 

RSU

 

RU

RU

R

 

R

RU

 

RU

 

RU

RU

 

RU

 

RU

RU

RU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

 

0

 

0

 

0

 

X

 

0

0

0

 

0

X

 

X

 

X

X

 

X

 

X

X

X

 

Register:

 

Isochronous receive context control

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only

 

 

 

 

 

 

Offset:

 

400h + (32 * n)

 

set register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

404h + (32 * n)

 

clear register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

X000 X0XXh

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 4±30. Isochronous Receive Context Control Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

 

FIELD NAME

 

 

TYPE

 

 

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When this bit is set, received packets are placed back-to-back to completely fill each receive buffer.

31

 

bufferFill

 

 

RSC

 

When this bit is cleared, each received packet is placed in a single buffer. If bit 28 (multiChanMode)

 

 

 

 

is set to 1, then this bit must also be set to 1. The value of this bit must not be changed while bit 10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(active) or bit 15 (run) is set.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When this bit is 1, received isochronous packets include the complete 4-byte isochronous packet

 

 

 

 

 

 

 

 

 

 

header seen by the link layer. The end of the packet is marked with xferStatus in the first doublet, and

30

 

isochHeader

 

 

RSC

 

a 16-bit timeStamp indicating the time of the most recently received (or sent) cycleStart packet.

 

 

 

 

When this bit is cleared, the packet header is stripped from received isochronous packets. The

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

packet header, if received, immediately precedes the packet payload. The value of this bit must not

 

 

 

 

 

 

 

 

 

 

be changed while bit 10 (active) or bit 15 (run) is set.

 

 

 

 

 

 

 

 

4±38

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Image 76
Texas Instruments TSB12LV26 Isochronous Transmit Context Command Pointer Register, Isochronous receive context control
Page 75 Page 77

TSB12LV26 specifications

The Texas Instruments TSB12LV26 is a high-performance, low-voltage transceiver designed for Serial Bus applications. It is widely recognized for its robust features and versatility, making it a popular choice among engineers and designers in various industries. One of the primary features of the TSB12LV26 is its support for high-speed data transmission, enabling it to operate at speeds up to 400 Mbps. This capability is essential for applications that demand rapid data transfer, such as in multimedia and communication systems.

The TSB12LV26 is part of the IEEE 1394 standard, also known as FireWire, which is widely used for connecting devices like digital cameras, external hard drives, and printers. The chip operates within a voltage range of 2.7V to 3.6V, making it suitable for low-power applications where energy efficiency is critical. The integration of advanced Low-Voltage Differential Signaling (LVDS) technology within the TSB12LV26 enhances signal integrity and reduces electromagnetic interference, resulting in more reliable performance over longer distances.

In terms of its physical characteristics, the TSB12LV26 is available in a compact 48-pin HTQFP package, which is beneficial for space-constrained designs. The device features a comprehensive set of input and output pins, allowing for flexible connectivity options. Additionally, the TSB12LV26 includes advanced power management features, including low-power modes that help extend battery life in portable devices.

Another significant advantage of the TSB12LV26 is its capability for peer-to-peer communication, enabling devices to connect and communicate directly without the need for a central controller. This functionality supports a wide range of device configurations and simplifies system architecture. Furthermore, the transceiver offers built-in support for asynchronous and isochronous data transfer, making it adaptable for various application requirements.

The TSB12LV26 also adheres to stringent EMI and ESD protection standards, ensuring reliable operation in challenging environments. With a rich feature set, excellent performance characteristics, and compliance with industry standards, the Texas Instruments TSB12LV26 remains an ideal choice for engineers looking to implement high-speed and reliable communication in their designs. Overall, it represents a significant advancement in the field of data transmission technology, making it a preferred component for numerous electronic applications.
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