Texas Instruments TSB12LV26 PCI Configuration Registers, Vendor ID Register, Register Name Offset

3.1 PCI Configuration Registers

The TSB12LV26 is a single-function PCI device. The configuration header is compliant with the PCI Local Bus Specification as a standard header. Table 3±2 illustrates the PCI configuration header that includes both the predefined portion of the configuration space and the user definable registers.

Table 3±2. PCI Configuration Register Map

	REGISTER NAME			OFFSET
Device ID		Vendor ID		00h
Status		Command		04h
	Class code		Revision ID	08h
BIST	Header type	Latency timer	Cache line size	0Ch
	OHCI registers base address			10h
	TI extension registers base address			14h
	Reserved			18h
	Reserved			1Ch
	Reserved			20h
	Reserved			24h
	Reserved			28h
Subsystem ID		Subsystem vendor ID		2Ch
	Reserved			30h
			PCI power
	Reserved		management	34h
			capabilities pointer
	Reserved			38h
Maximum latency	Minimum grant	Interrupt pin	Interrupt line	3Ch
	PCI OHCI control register			40h
Power management capabilities		Next item pointer	Capability ID	44h
PM data	PMCSR_BSE	Power management CSR		48h
	Reserved			4Ch±ECh
	PCI miscellaneous configuration register			F0h
	Link_Enhancements register			F4h
Subsystem ID alias		Subsystem vendor ID alias		F8h
GPIO3	GPIO2	Reserved		FCh

3.2 Vendor ID Register

The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device. The vendor ID assigned to Texas Instruments is 104Ch.

Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Name								Vendor ID
Type	R	R	R	R	R	R	R	R	R	R	R	R	R	R	R	R
Default	0	0	0	1	0	0	0	0	0	1	0	0	1	1	0	0

Register: Vendor ID

Type: Read-only

Offset: 00h

Default: 104Ch

3±3