±3. Power Supply Terminals | Texas Instruments TSB12LV26 manual

Table 2±2. Signal Names Sorted Alphanumerically to Terminal Number

TERMINAL NAME			NO.	TERMINAL NAME			NO.	TERMINAL NAME																	NO.	TERMINAL NAME			NO.

CYCLEIN			78	PCI_AD11			59						PCI_CLK												12	PHY_DATA7			81

CYCLEOUT			77	PCI_AD12			58																		7	PHY_LINKON			98
CYCLEOUT			77	PCI_AD12			58		PCI_CLKRUN																7	PHY_LINKON			98

	GND		1	PCI_AD13			57																		47	PHY_LPS			99
	GND		1	PCI_AD13			57		PCI_DEVSEL																47	PHY_LPS			99
	GND		11	PCI_AD14			56																		43	PHY_LREQ			97
	GND		11	PCI_AD14			56			PCI_FRAME															43	PHY_LREQ			97

	GND		24	PCI_AD15			54																		14	PHY_SCLK			95
	GND		24	PCI_AD15			54						PCI_GNT												14	PHY_SCLK			95
	GND		30	PCI_AD16			40			PCI_IDSEL															29				79
	GND		30	PCI_AD16			40			PCI_IDSEL															29		REG_EN		79

	GND		50	PCI_AD17			38																		8		REG18		42
	GND		50	PCI_AD17			38						PCI_INTA												8		REG18		42

	GND		60	PCI_AD18			37																		44		REG18		100
	GND		60	PCI_AD18			37					PCI_IRDY													44		REG18		100

	GND		75	PCI_AD19			36						PCI_PAR												52		SCL		4

	GND		83	PCI_AD20			34																		49		SDA		5
	GND		83	PCI_AD20			34				PCI_PERR														49		SDA		5

	GND		94	PCI_AD21			33																		17		VCCP		6
	GND		94	PCI_AD21			33						PCI_PME												17		VCCP		6
	GPIO2		2	PCI_AD22			32																		15		VCCP		16
	GPIO2		2	PCI_AD22			32						PCI_REQ												15		VCCP		16
	GPIO3		3	PCI_AD23			31																		76		VCCP		39
	GPIO3		3	PCI_AD23			31						PCI_RST												76		VCCP		39
			10	PCI_AD24			27																		51		VCCP		63
	G_RST		10	PCI_AD24			27				PCI_SERR														51		VCCP		63
PCI_AD0			74	PCI_AD25			26																		48		VCCP		87
PCI_AD0			74	PCI_AD25			26					PCI_STOP													48		VCCP		87
PCI_AD1			73	PCI_AD26			25																		45		3.3 VCC		9
PCI_AD1			73	PCI_AD26			25					PCI_TRDY													45		3.3 VCC		9
PCI_AD2			72	PCI_AD27			23			PHY_CTL0															93		3.3 VCC		13
PCI_AD3			71	PCI_AD28			22			PHY_CTL1															92		3.3 VCC		20
PCI_AD4			69	PCI_AD29			21			PHY_DATA0															90		3.3 VCC		35
PCI_AD5			68	PCI_AD30			19			PHY_DATA1															89		3.3 VCC		46
PCI_AD6			67	PCI_AD31			18			PHY_DATA2															88		3.3 VCC		55
PCI_AD7			66
PCI_AD7			66	PCI_C/BE0			65			PHY_DATA3															86		3.3 VCC		70
PCI_AD8			64				53			PHY_DATA4															85		3.3 VCC		80
PCI_AD8			64	PCI_C/BE1			53			PHY_DATA4															85		3.3 VCC		80
PCI_AD9			62				41			PHY_DATA5															84		3.3 VCC		91
PCI_AD9			62	PCI_C/BE2			41			PHY_DATA5															84		3.3 VCC		91
PCI_AD10			61				28			PHY_DATA6															82		3.3 VCC		96
PCI_AD10			61	PCI_C/BE3			28			PHY_DATA6															82		3.3 VCC		96

The terminals in Table 2±3 through Table 2±8 are grouped in tables by functionality, such as PCI system function and power supply function. The terminal numbers are also listed for convenient reference.

				Table 2±3. Power Supply Terminals
	TERMINAL		I/O	DESCRIPTION

	NAME	NO.
	NAME	NO.

		1, 11, 24, 30,
	GND	50, 60, 75, 83,	I	Device ground terminals
		94

	VCCP	6, 16, 39, 63,	I	PCI signaling clamp voltage power input. PCI signals are clamped per the PCI Local Bus Specification.
	VCCP	87	I
		87

		9, 13, 20, 35,
	3.3 VCC	46, 55, 70, 80,	I	3.3-V power supply terminals
		91, 96

2±3

Image 15

Texas Instruments TSB12LV26 manual ±2. Signal Names Sorted Alphanumerically to Terminal Number, ±3. Power Supply Terminals

TSB12LV26 specifications

The Texas Instruments TSB12LV26 is a high-performance, low-voltage transceiver designed for Serial Bus applications. It is widely recognized for its robust features and versatility, making it a popular choice among engineers and designers in various industries. One of the primary features of the TSB12LV26 is its support for high-speed data transmission, enabling it to operate at speeds up to 400 Mbps. This capability is essential for applications that demand rapid data transfer, such as in multimedia and communication systems.

The TSB12LV26 is part of the IEEE 1394 standard, also known as FireWire, which is widely used for connecting devices like digital cameras, external hard drives, and printers. The chip operates within a voltage range of 2.7V to 3.6V, making it suitable for low-power applications where energy efficiency is critical. The integration of advanced Low-Voltage Differential Signaling (LVDS) technology within the TSB12LV26 enhances signal integrity and reduces electromagnetic interference, resulting in more reliable performance over longer distances.

In terms of its physical characteristics, the TSB12LV26 is available in a compact 48-pin HTQFP package, which is beneficial for space-constrained designs. The device features a comprehensive set of input and output pins, allowing for flexible connectivity options. Additionally, the TSB12LV26 includes advanced power management features, including low-power modes that help extend battery life in portable devices.

Another significant advantage of the TSB12LV26 is its capability for peer-to-peer communication, enabling devices to connect and communicate directly without the need for a central controller. This functionality supports a wide range of device configurations and simplifies system architecture. Furthermore, the transceiver offers built-in support for asynchronous and isochronous data transfer, making it adaptable for various application requirements.

The TSB12LV26 also adheres to stringent EMI and ESD protection standards, ensuring reliable operation in challenging environments. With a rich feature set, excellent performance characteristics, and compliance with industry standards, the Texas Instruments TSB12LV26 remains an ideal choice for engineers looking to implement high-speed and reliable communication in their designs. Overall, it represents a significant advancement in the field of data transmission technology, making it a preferred component for numerous electronic applications.

Contents

Data Manual SLLS366A TSB12LV26 Important Notice Contents Page Mechanical Information List of Illustrations Vii List of Tables Viii Description Features OHCI-Lynx PCI-Based Ieee 1394 Host Controller Related DocumentsOrdering Information Ordering Number Name Voltage Package CCP PZ Package TOP ViewVccp Pciclkrun Pciinta 3.3 VCC Vccp Terminal Name ±1. Signals Sorted by Terminal Number ±2. Signal Names Sorted Alphanumerically to Terminal Number ±3. Power Supply TerminalsTerminal Description Name As open-drain ±4. PCI System TerminalsPCIRST, terminal Pciclk ±5. PCI Address and Data Terminals During the data phase, AD31±AD0 contain data Pcitrdy ±6. PCI Interface Control TerminalsPcic BE0 Irdy ±8. Miscellaneous Terminals ±7. Ieee 1394 PHY/Link TerminalsPage Access TAG Name Meaning ±1. Bit Field Access Tag Descriptions ±1. TSB12LV26 Block Diagram Register Name Offset PCI Configuration Registers±2. PCI Configuration Register Map Vendor ID Register Device ID Register Command RegisterCommand ±3. Command Register Description Status Register Status±4. Status Register Description Class code and revision ID Latency Timer and Class Cache Line Size RegisterLatency timer and class cache line size Class Code and Revision ID Register Ohci Base Address Register Header Type and Bist Register Subsystem identification TI Extension Base Address RegisterSubsystem Identification Register TI extension base address Register Interrupt line and pin Power Management Capabilities Pointer RegisterRegister Power management capabilities pointer Interrupt Line and Pin Register Ohci Control Register Mingnt and Maxlat Register Capabilityid Capability ID and Next Item Pointer RegisterRegister Capability ID and next item pointer Nextitem Power Management Capabilities Register Register Power management capabilities±14. Power Management Capabilities Register Description Power management extension Power Management Control and Status RegisterPower Management Extension Register Power management control and status Miscellaneous Configuration Register Miscellaneous configuration±17. Miscellaneous Configuration Register Link Enhancement Control Register Link enhancement control±18. Link Enhancement Control Register Description Subdevid Subsystem Access RegisterSubsystem access ±19. Subsystem Access Register Description Gpio Control Register Gpio control±20. Gpio Control Register Description ±18 ±1. Ohci Register Map DMA Context Register Name Abbreviation OffsetGuid ROM Guidrom Physical request filter low PhysicalRequestFilterLoSet IsoRecvIntEventClearIsochronous receive interrupt mask IsoRecvIntMaskSet PhysicalRequestFilterHiClear Asynchronous context control ContextControlSet Isochronous transmit context commandIsochronous receive context command CommandPtr 40Ch + 32*n Pointer Context match ContextMatch Ohci Version Register Ohci version±2. Ohci Version Register Description RSU Guid ROM Register±3. Guid ROM Register Description Guid ROM ±4. Asynchronous Transmit Retries Register Description Asynchronous Transmit Retries RegisterCSR Data Register Asynchronous transmit retries CSR control CSR Compare RegisterCSR Control Register CSR compare Bus Identification Register Configuration ROM Header RegisterConfiguration ROM header ±6. Configuration ROM Header Register Description Bus Options Register Bus options±7. Bus Options Register Description Guid low Guid High RegisterGuid Low Register Guid high Posted Write Address Low Register Configuration ROM Mapping RegisterConfiguration ROM mapping ±8. Configuration ROM Mapping Register Description Vendor ID Posted Write Address High RegisterPosted write address high ±9. Posted Write Address High Register Description Host Controller Control Register Host controller control±10. Host Controller Control Register Description Self-ID count Self-ID Buffer Pointer RegisterSelf-ID Count Register Self ID-buffer pointer Isochronous receive channel mask high Isochronous Receive Channel Mask High Register Isochronous receive channel mask low Isochronous Receive Channel Mask Low Register Interrupt Event Register Interrupt event±14. Interrupt Event Register Description Arrq Rscu Arrs Rscu Rscu RSC Interrupt Mask RegisterInterrupt mask ±15. Interrupt Mask Register Description Isochronous transmit interrupt event Isochronous Transmit Interrupt Event Register Isochronous transmit interrupt mask Isochronous Transmit Interrupt Mask RegisterIsochronous transmit interrupt mask ±21 Isochronous receive interrupt mask Isochronous Receive Interrupt Event RegisterIsochronous Receive Interrupt Mask Register Isochronous receive interrupt event Fairness control Fairness Control RegisterFairness control ±18. Fairness Control Register Description Link Control Register Link control±19. Link Control Register Description CPS Node Identification RegisterNode identification ±20. Node Identification Register Description PHY Layer Control Register PHY layer control±21. PHY Control Register Description 24±12 Isochronous Cycle Timer RegisterIsochronous cycle timer ±22. Isochronous Cycle Timer Register Description Asynchronous Request Filter High Register Asynchronous request filter high±23. Asynchronous Request Filter High Register Description ±29 ±30 Asynchronous Request Filter Low RegisterAsynchronous request filter low ±24. Asynchronous Request Filter Low Register Description Are accepted Physical Request Filter High RegisterPhysical request filter high ±25. Physical Request Filter High Register Description ±32 Physical request filter low Physical Request Filter Low RegisterPhysical request filter low ±26. Physical Request Filter Low Register Description ±34 Physical Upper Bound Register Optional RegisterPhysical upper bound Physical upper bound Rscu RSU Asynchronous Context Control RegisterAsynchronous context control ±27. Asynchronous Context Control Register Description Asynchronous Context Command Pointer Register Asynchronous context command pointer31±4 DescriptorAddress Isochronous Transmit Context Control Register Isochronous transmit context controlRSC RSU Isochronous receive context control Isochronous Transmit Context Command Pointer RegisterIsochronous transmit context command pointer Isochronous Receive Context Control Register Match register see .43 is ignored CycleMatchEnableReserved. Bits 27±16 return 0s when read MultiChanMode ±40 Isochronous Receive Context Command Pointer RegisterIsochronous receive context command pointer Isochronous receive context command pointer ±31. Isochronous Receive Context Match Register Description When the command descriptor w field is set to 11bIsochronous Receive Context Match Register Isochronous receive context match ±42 Gpio Interface Page ±1. Registers and Bits Loadable through Serial ROM ROM Offset OHCI/PCI Offset Register Bits Loaded From ROM13h PCI register 40h PCI Ohci register ±2. Serial ROM Map Byte Byte Description AddressRsvd PME Absolute Maximum Ratings Over Operating Temperature Ranges² Electrical Characteristics Recommended Operating Conditions Operation MIN NOMUnit Parameter Measured MIN TYP MAX Unit Switching Characteristics for PCI Interface§Switching Characteristics for PHY-Link Interface§ Operation Test MIN MAX Unit ConditionsPage PZ S-PQFP-G100 Mechanical InformationPage Important Notice