Texas Instruments TSB12LV26 manual Link Enhancement Control Register, Link enhancement control

3.21 Link Enhancement Control Register

The link enhancement control register implements TI proprietary bits that are initialized by software or by a serial ROM, if present. After these bits are set, their functionality is enabled only if bit 22 (aPhyEnhanceEnable) in the host controller control register (OHCI offset 50h/54h, see Section 4.16) is set. See Table 3±18 for a complete description of the register contents.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

Link enhancement control

Type

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Link enhancement control

Type

R

R

R/W

R/W

R

R

R

R

R/W

R

R

R

R

R/W

R/W

R

Default

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

Register:

Link enhancement control

Type:

Read/Write, Read-only

Offset:

F4h

Default:

0000 1000h

Table 3±18. Link Enhancement Control Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31±14

RSVD

R

Reserved. Bits 31±14 return 0s when read.

This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the

TSB12LV26 retries the packet, it uses a 2-Kbyte threshold resulting in a store-and-forward operation.

00 = Threshold ~ 2K bytes resulting in a store-and-forward operation

01 = Threshold ~ 1.7K bytes (default)

10 = Threshold ~ 1K bytes

11 = Threshold ~ 512 bytes

These bits fine-tune the asynchronous transmit threshold. For most applications the 1.7K threshold

is optimal. Changing this value may increase or decrease the 1394 latency depending on the average

13±12

atx_thresh

R/W

PCI bus latency.

Setting the AT threshold to 1.7K, 1K, or 512 bytes results in data being transmitted at these thresholds,

or when an entire packet has been checked into the FIFO. If the packet to be transmitted is larger than

the AT threshold, then the remaning data must be received before the AT FIFO is emptied; otherwise,

an underrun condition will occur, resulting in a packet error at the receiving node. As a result, the link

will then commence store-and-forward operation, i.e., wait until it has the complete packet in the FIFO

before retransmitting it on the second attempt, to ensure delivery.

An AT threshold of 2K results in store-and-forward operation, which means that asynchronous data

will not be transmitted until an end-of-packet token is received. Restated, setting the AT threshold to

2K results in only complete packets being transmitted.

11±8

RSVD

R

Reserved. Bits 11±8 return 0s when read.

7

enab_unfair

R/W

Enable asynchronous priority requests. OHCI-Lynx compatible. Setting this bit to 1 enables the link

to respond to requests with priority arbitration. It is recommended that this bit be set to 1.

This bit is not assigned in the TSB12LV26 follow-on products since this bit location loaded by the serial

6

RSVD

R

ROM from the enhancements field corresponds to bit 23 (programPhyEnable) in the host controller

control register (OHCI offset 50h/54h, see Section 4.16).

5±3

RSVD

R

Reserved. Bits 5±3 return 0s when read.

Enable insert idle. OHCI-Lynx compatible. When the PHY has control of the Ct[0:1] control lines and

D[0:8] data lines and the link requests control, the PHY drives 11b on the Ct[0:1] lines. The link can

2

enab_insert_idle

R/W

then start driving these lines immediately. Setting this bit to 1 inserts an idle state, so the link waits one

clock cycle before it starts driving the lines (turnaround time). It is recommended that this bit be set to

1.

3±15