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Texas Instruments TSB12LV26 manual Isochronous Receive Channel Mask Low Register

Models: TSB12LV26

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Table 4±12. Isochronous Receive Channel Mask High Register Description (Continued)

BIT	FIELD NAME	TYPE	DESCRIPTION

6	isoChannel38	RSC	When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 38.

5	isoChannel37	RSC	When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 37.

4	isoChannel36	RSC	When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 36.

3	isoChannel35	RSC	When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 35.

2	isoChannel34	RSC	When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 34.

1	isoChannel33	RSC	When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 33.

0	isoChannel32	RSC	When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 32.

4.20 Isochronous Receive Channel Mask Low Register

The isochronous receive channel mask low set/clear register is used to enable packet receives from the lower 32 isochronous data channels. See Table 4±13 for a complete description of the register contents.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

Isochronous receive channel mask low

Type

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

Default

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Isochronous receive channel mask low

Type

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

Default

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

Register:

Isochronous receive channel mask low

Type:

Read/Set/Clear

Offset:

78h

set register

7Ch

clear register

	Default:	XXXX XXXXh
	Table 4±13. Isochronous Receive Channel Mask Low Register Description

BIT	FIELD NAME		TYPE	DESCRIPTION

31	isoChannel31		RSC	When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 31.

30	isoChannel30		RSC	When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 30.

				Bits 29 through 2 follow the same pattern.

1	isoChannel1		RSC	When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 1.

0	isoChannel0		RSC	When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 0.

4±16

Image 54

Texas Instruments TSB12LV26 manual Isochronous Receive Channel Mask Low Register, Isochronous receive channel mask low

Contents

Data Manual SLLS366A TSB12LV26 Important Notice Contents Page Mechanical Information List of Illustrations List of Tables ViiViii Features DescriptionOrdering Number Name Voltage Package Related DocumentsOrdering Information OHCI-Lynx PCI-Based Ieee 1394 Host ControllerVccp PZ Package TOP ViewVccp Pciclkrun Pciinta 3.3 VCC CCP±1. Signals Sorted by Terminal Number Terminal Name±2. Signal Names Sorted Alphanumerically to Terminal Number ±3. Power Supply TerminalsTerminal Description Name Pciclk ±4. PCI System TerminalsPCIRST, terminal As open-drainDuring the data phase, AD31±AD0 contain data ±5. PCI Address and Data TerminalsIrdy ±6. PCI Interface Control TerminalsPcic BE0 Pcitrdy±7. Ieee 1394 PHY/Link Terminals ±8. Miscellaneous TerminalsPage ±1. Bit Field Access Tag Descriptions Access TAG Name Meaning±1. TSB12LV26 Block Diagram Vendor ID Register PCI Configuration Registers±2. PCI Configuration Register Map Register Name Offset±3. Command Register Description Command RegisterCommand Device ID RegisterStatus Register Status±4. Status Register Description Class Code and Revision ID Register Latency Timer and Class Cache Line Size RegisterLatency timer and class cache line size Class code and revision IDHeader Type and Bist Register Ohci Base Address RegisterTI extension base address TI Extension Base Address RegisterSubsystem Identification Register Subsystem identificationInterrupt Line and Pin Register Power Management Capabilities Pointer RegisterRegister Power management capabilities pointer Register Interrupt line and pinMingnt and Maxlat Register Ohci Control RegisterNextitem Capability ID and Next Item Pointer RegisterRegister Capability ID and next item pointer CapabilityidPower Management Capabilities Register Register Power management capabilities±14. Power Management Capabilities Register Description Power management control and status Power Management Control and Status RegisterPower Management Extension Register Power management extensionMiscellaneous Configuration Register Miscellaneous configuration±17. Miscellaneous Configuration Register Link Enhancement Control Register Link enhancement control±18. Link Enhancement Control Register Description ±19. Subsystem Access Register Description Subsystem Access RegisterSubsystem access SubdevidGpio Control Register Gpio control±20. Gpio Control Register Description ±18 ±1. Ohci Register Map DMA Context Register Name Abbreviation OffsetGuid ROM Guidrom PhysicalRequestFilterHiClear IsoRecvIntEventClearIsochronous receive interrupt mask IsoRecvIntMaskSet Physical request filter low PhysicalRequestFilterLoSetCommandPtr 40Ch + 32*n Pointer Context match ContextMatch Isochronous transmit context commandIsochronous receive context command Asynchronous context control ContextControlSetOhci Version Register Ohci version±2. Ohci Version Register Description Guid ROM Guid ROM Register±3. Guid ROM Register Description RSUAsynchronous transmit retries Asynchronous Transmit Retries RegisterCSR Data Register ±4. Asynchronous Transmit Retries Register DescriptionCSR compare CSR Compare RegisterCSR Control Register CSR control±6. Configuration ROM Header Register Description Configuration ROM Header RegisterConfiguration ROM header Bus Identification RegisterBus Options Register Bus options±7. Bus Options Register Description Guid high Guid High RegisterGuid Low Register Guid low±8. Configuration ROM Mapping Register Description Configuration ROM Mapping RegisterConfiguration ROM mapping Posted Write Address Low Register±9. Posted Write Address High Register Description Posted Write Address High RegisterPosted write address high Vendor IDHost Controller Control Register Host controller control±10. Host Controller Control Register Description Self ID-buffer pointer Self-ID Buffer Pointer RegisterSelf-ID Count Register Self-ID countIsochronous Receive Channel Mask High Register Isochronous receive channel mask highIsochronous Receive Channel Mask Low Register Isochronous receive channel mask lowInterrupt Event Register Interrupt event±14. Interrupt Event Register Description Arrs Rscu Arrq Rscu±15. Interrupt Mask Register Description Interrupt Mask RegisterInterrupt mask Rscu RSCIsochronous Transmit Interrupt Event Register Isochronous transmit interrupt event±21 Isochronous Transmit Interrupt Mask RegisterIsochronous transmit interrupt mask Isochronous transmit interrupt maskIsochronous receive interrupt event Isochronous Receive Interrupt Event RegisterIsochronous Receive Interrupt Mask Register Isochronous receive interrupt mask±18. Fairness Control Register Description Fairness Control RegisterFairness control Fairness controlLink Control Register Link control±19. Link Control Register Description ±20. Node Identification Register Description Node Identification RegisterNode identification CPSPHY Layer Control Register PHY layer control±21. PHY Control Register Description ±22. Isochronous Cycle Timer Register Description Isochronous Cycle Timer RegisterIsochronous cycle timer 24±12Asynchronous Request Filter High Register Asynchronous request filter high±23. Asynchronous Request Filter High Register Description ±29 ±24. Asynchronous Request Filter Low Register Description Asynchronous Request Filter Low RegisterAsynchronous request filter low ±30±25. Physical Request Filter High Register Description Physical Request Filter High RegisterPhysical request filter high Are accepted±32 ±26. Physical Request Filter Low Register Description Physical Request Filter Low RegisterPhysical request filter low Physical request filter lowPhysical upper bound Physical Upper Bound Register Optional RegisterPhysical upper bound ±34±27. Asynchronous Context Control Register Description Asynchronous Context Control RegisterAsynchronous context control Rscu RSUAsynchronous Context Command Pointer Register Asynchronous context command pointer31±4 DescriptorAddress Isochronous Transmit Context Control Register Isochronous transmit context controlRSC RSU Isochronous Receive Context Control Register Isochronous Transmit Context Command Pointer RegisterIsochronous transmit context command pointer Isochronous receive context controlMultiChanMode CycleMatchEnableReserved. Bits 27±16 return 0s when read Match register see .43 is ignoredIsochronous receive context command pointer Isochronous Receive Context Command Pointer RegisterIsochronous receive context command pointer ±40Isochronous receive context match When the command descriptor w field is set to 11bIsochronous Receive Context Match Register ±31. Isochronous Receive Context Match Register Description±42 Gpio Interface Page ±1. Registers and Bits Loadable through Serial ROM ROM Offset OHCI/PCI Offset Register Bits Loaded From ROM13h PCI register 40h PCI Ohci register ±2. Serial ROM Map Byte Byte Description AddressRsvd PME Electrical Characteristics Absolute Maximum Ratings Over Operating Temperature Ranges²Recommended Operating Conditions Operation MIN NOMUnit Operation Test MIN MAX Unit Conditions Switching Characteristics for PCI Interface§Switching Characteristics for PHY-Link Interface§ Parameter Measured MIN TYP MAX UnitPage Mechanical Information PZ S-PQFP-G100Page Important Notice