Table 4±12. Isochronous Receive Channel Mask High Register Description (Continued)

BIT

FIELD NAME

TYPE

DESCRIPTION

 

 

 

 

6

isoChannel38

RSC

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 38.

 

 

 

 

5

isoChannel37

RSC

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 37.

 

 

 

 

4

isoChannel36

RSC

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 36.

 

 

 

 

3

isoChannel35

RSC

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 35.

 

 

 

 

2

isoChannel34

RSC

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 34.

 

 

 

 

1

isoChannel33

RSC

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 33.

 

 

 

 

0

isoChannel32

RSC

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 32.

 

 

 

 

4.20 Isochronous Receive Channel Mask Low Register

The isochronous receive channel mask low set/clear register is used to enable packet receives from the lower 32 isochronous data channels. See Table 4±13 for a complete description of the register contents.

Bit

31

 

30

29

28

27

 

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

Isochronous receive channel mask low

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RSC

 

RSC

RSC

RSC

RSC

 

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

X

 

X

X

X

X

 

X

X

X

X

X

X

X

X

X

X

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

15

 

14

13

12

11

 

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

Isochronous receive channel mask low

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RSC

 

RSC

RSC

RSC

RSC

 

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

X

 

X

X

X

X

 

X

X

X

X

X

X

X

X

X

X

X

 

Register:

Isochronous receive channel mask low

 

 

 

 

 

 

 

 

Type:

 

Read/Set/Clear

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

78h

set register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7Ch

clear register

 

 

 

 

 

 

 

 

 

 

 

Default:

XXXX XXXXh

 

Table 4±13. Isochronous Receive Channel Mask Low Register Description

 

 

 

 

 

BIT

FIELD NAME

 

TYPE

DESCRIPTION

 

 

 

 

 

31

isoChannel31

 

RSC

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 31.

 

 

 

 

 

30

isoChannel30

 

RSC

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 30.

 

 

 

 

 

 

 

 

 

Bits 29 through 2 follow the same pattern.

 

 

 

 

 

1

isoChannel1

 

RSC

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 1.

 

 

 

 

 

0

isoChannel0

 

RSC

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 0.

 

 

 

 

 

4±16

Page 53 Page 55
Page 54
Image 54
Texas Instruments TSB12LV26 manual Isochronous Receive Channel Mask Low Register, Isochronous receive channel mask low
Page 53 Page 55

TSB12LV26 specifications

The Texas Instruments TSB12LV26 is a high-performance, low-voltage transceiver designed for Serial Bus applications. It is widely recognized for its robust features and versatility, making it a popular choice among engineers and designers in various industries. One of the primary features of the TSB12LV26 is its support for high-speed data transmission, enabling it to operate at speeds up to 400 Mbps. This capability is essential for applications that demand rapid data transfer, such as in multimedia and communication systems.

The TSB12LV26 is part of the IEEE 1394 standard, also known as FireWire, which is widely used for connecting devices like digital cameras, external hard drives, and printers. The chip operates within a voltage range of 2.7V to 3.6V, making it suitable for low-power applications where energy efficiency is critical. The integration of advanced Low-Voltage Differential Signaling (LVDS) technology within the TSB12LV26 enhances signal integrity and reduces electromagnetic interference, resulting in more reliable performance over longer distances.

In terms of its physical characteristics, the TSB12LV26 is available in a compact 48-pin HTQFP package, which is beneficial for space-constrained designs. The device features a comprehensive set of input and output pins, allowing for flexible connectivity options. Additionally, the TSB12LV26 includes advanced power management features, including low-power modes that help extend battery life in portable devices.

Another significant advantage of the TSB12LV26 is its capability for peer-to-peer communication, enabling devices to connect and communicate directly without the need for a central controller. This functionality supports a wide range of device configurations and simplifies system architecture. Furthermore, the transceiver offers built-in support for asynchronous and isochronous data transfer, making it adaptable for various application requirements.

The TSB12LV26 also adheres to stringent EMI and ESD protection standards, ensuring reliable operation in challenging environments. With a rich feature set, excellent performance characteristics, and compliance with industry standards, the Texas Instruments TSB12LV26 remains an ideal choice for engineers looking to implement high-speed and reliable communication in their designs. Overall, it represents a significant advancement in the field of data transmission technology, making it a preferred component for numerous electronic applications.
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