Texas Instruments TSB12LV26 manual Fairness Control Register, Fairness control

4.27 Fairness Control Register

The fairness control register provides a mechanism by which software can direct the host controller to transmit multiple asynchronous requests during a fairness interval. See Table 4±18 for a complete description of the register contents.

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Name								Fairness control
Type	R	R	R	R	R	R	R	R	R	R	R	R	R	R	R	R
Default	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Bit	15	14	13	12		11	10	9	8	7	6	5	4	3	2	1	0
Name									Fairness control
Type	R	R	R		R	R	R	R	R	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Default	0	0	0		0	0	0	0	0	0	0	0	0	0	0	0	0
	Register:		Fairness control
	Type:		Read-only, Read/Write
	Offset:		DCh
	Default:		0000 0000h
					Table 4±18. Fairness Control Register Description
BIT	FIELD NAME			TYPE							DESCRIPTION
31±8	RSVD				R	Reserved. Bits 31±8 return 0s when read.
7±0	pri_req			R/W		This field specifies the maximum number of priority arbitration requests for asynchronous request
						packets that the link is permitted to make of the PHY during a fairness interval.

4±23