4 OHCI Registers

The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory-mapped into a 2-Kbyte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space (see Section 3.9). These registers are the primary interface for controlling the TSB12LV26 IEEE 1394 link function.

This section provides the register interface and bit descriptions. There are several set/clear register pairs in this programming model, which are implemented to solve various issues with typical read-modify-write control registers. There are two addresses for a set/clear register: RegisterSet and RegisterClear. Refer to Table 4±1 for an illustration. A 1 bit written to RegisterSet causes the corresponding bit in the set/clear register to be set, while a 0 bit leaves the corresponding bit unaffected. A 1 bit written to RegisterClear causes the corresponding bit in the set/clear register to be cleared, while a 0 bit leaves the corresponding bit in the set/clear register unaffected.

Typically, a read from either RegisterSet or RegisterClear returns the contents of the set or clear register, respectively. However, sometimes reading the RegisterClear provides a masked version of the set or clear register. The interrupt event register is an example of this behavior.

Table 4±1. OHCI Register Map

DMA CONTEXT

REGISTER NAME

ABBREVIATION

OFFSET

 

 

 

 

Ð

OHCI version

Version

00h

 

 

 

 

 

GUID ROM

GUID_ROM

04h

 

 

 

 

 

Asynchronous transmit retries

ATRetries

08h

 

 

 

 

 

CSR data

CSRData

0Ch

 

 

 

 

 

CSR compare data

CSRCompareData

10h

 

 

 

 

 

CSR control

CSRControl

14h

 

 

 

 

 

Configuration ROM header

ConfigROMhdr

18h

 

 

 

 

 

Bus identification

BusID

1Ch

 

 

 

 

 

Bus options

BusOptions

20h

 

 

 

 

 

GUID high

GUIDHi

24h

 

 

 

 

 

GUID low

GUIDLo

28h

 

 

 

 

 

Reserved

Ð

2Ch±30h

 

 

 

 

 

Configuration ROM map

ConfigROMmap

34h

 

 

 

 

 

Posted write address low

PostedWriteAddressLo

38h

 

 

 

 

 

Posted write address high

PostedWriteAddressHi

3Ch

 

 

 

 

 

Vendor identification

VendorID

40h±4Ch

 

 

 

 

 

Host controller control

HCControlSet

50h

 

 

 

 

HCControlClr

54h

 

 

 

 

 

 

 

Reserved

Ð

58h±5Ch

4±1

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Image 39
Texas Instruments TSB12LV26 manual ±1. Ohci Register Map, DMA Context Register Name Abbreviation Offset, Guid ROM Guidrom
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TSB12LV26 specifications

The Texas Instruments TSB12LV26 is a high-performance, low-voltage transceiver designed for Serial Bus applications. It is widely recognized for its robust features and versatility, making it a popular choice among engineers and designers in various industries. One of the primary features of the TSB12LV26 is its support for high-speed data transmission, enabling it to operate at speeds up to 400 Mbps. This capability is essential for applications that demand rapid data transfer, such as in multimedia and communication systems.

The TSB12LV26 is part of the IEEE 1394 standard, also known as FireWire, which is widely used for connecting devices like digital cameras, external hard drives, and printers. The chip operates within a voltage range of 2.7V to 3.6V, making it suitable for low-power applications where energy efficiency is critical. The integration of advanced Low-Voltage Differential Signaling (LVDS) technology within the TSB12LV26 enhances signal integrity and reduces electromagnetic interference, resulting in more reliable performance over longer distances.

In terms of its physical characteristics, the TSB12LV26 is available in a compact 48-pin HTQFP package, which is beneficial for space-constrained designs. The device features a comprehensive set of input and output pins, allowing for flexible connectivity options. Additionally, the TSB12LV26 includes advanced power management features, including low-power modes that help extend battery life in portable devices.

Another significant advantage of the TSB12LV26 is its capability for peer-to-peer communication, enabling devices to connect and communicate directly without the need for a central controller. This functionality supports a wide range of device configurations and simplifies system architecture. Furthermore, the transceiver offers built-in support for asynchronous and isochronous data transfer, making it adaptable for various application requirements.

The TSB12LV26 also adheres to stringent EMI and ESD protection standards, ensuring reliable operation in challenging environments. With a rich feature set, excellent performance characteristics, and compliance with industry standards, the Texas Instruments TSB12LV26 remains an ideal choice for engineers looking to implement high-speed and reliable communication in their designs. Overall, it represents a significant advancement in the field of data transmission technology, making it a preferred component for numerous electronic applications.
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