Texas Instruments TSB12LV26 manual ±7. Ieee 1394 PHY/Link Terminals, ±8. Miscellaneous Terminals

			Table 2±7. IEEE 1394 PHY/Link Terminals
TERMINAL		I/O	DESCRIPTION
NAME	NO.
PHY_CTL1	92		PHY-link interface control. These bidirectional signals control passage of information between the two devices.
		I/O	The TSB12LV26 can only drive these terminals after the PHY has granted permission following a link request
PHY_CTL0	93
			(PHY_LREQ).
PHY_DATA7	81
PHY_DATA6	82
PHY_DATA5	84		PHY-link interface data. These bidirectional signals pass data between the TSB12LV26 and the PHY device.
PHY_DATA4	85	I/O	These terminals are driven by the TSB12LV26 on transmissions and are driven by the PHY on reception. Only
PHY_DATA3	86		PHY_DATA1±PHY_DATA0 are valid for 100-Mbit speeds, PHY_DATA3±PHY_DATA0 are valid for 200-Mbit
PHY_DATA2	88		speeds, and PHY_DATA7±PHY_DATA0 are valid for 400-Mbit speeds.
PHY_DATA1	89
PHY_DATA0	90
			LinkOn wake indication. The PHY_LINKON signal is pulsed by the PHY to activate the link, and 3.3-V signaling
PHY_LINKON	98	I/O	is required.
			When connected to the TSB41LV0X C/LKON terminal, a 1-kΩseries resistor is required between the link and
			PHY.
PHY_LPS	99	I/O	Link power status. The PHY_LPS signal is asserted when the link is powered on, and 3.3-V signaling is
			required.
PHY_LREQ	97	O	Link request. This signal is driven by the TSB12LV26 to initiate a request for the PHY to perform some service.
PHY_SCLK	95	I	System clock. This input from the PHY provides a 49.152-MHz clock signal for data synchronization.

			Table 2±8. Miscellaneous Terminals
TERMINAL		I/O	DESCRIPTION
NAME	NO.
CYCLEOUT	77	I/O	This terminal provides an 8-kHz cycle timer synchronization signal.
			The CYCLEIN terminal allows an external 8-kHz clock to be used as a cycle timer for synchronization with other
CYCLEIN	78	I/O	system devices.
			If this terminal is not implemented, then it should be pulled high to the link VCC through a 4.7-kΩresistor.
GPIO2	2	I/O	General-purpose I/O [2]. This terminal defaults as an input and if it is not implemented, then it is recommended
			that it be pulled low to ground with a 220-Ωresistor.
GPIO3	3	I/O	General-purpose I/O [3]. This terminal defaults as an input and if it is not implemented, then it is recommended
			that it be pulled low to ground with a 220-Ωresistor.
	79	I	Regulator enable. This terminal is pulled low to ground through a 220-Ωresistor.
REG_EN
REG18	42	I	The REG18 terminals are connected to a 0.01 ∝F capacitor which, in turn, is connected to ground. The
	100		capacitor provides a local bypass for the internal core voltage.
			Serial clock. The TSB12LV26 determines whether a two-wire serial ROM is implemented at reset. If a two-wire
			serial ROM is implemented, then this terminal provides the SCL serial clock signaling.
SCL	4	I/O	This terminal is implemented as open-drain, and for normal operation (a ROM is implemented in the design),
			this terminal should be pulled high to the ROM VCC with a 2.7-kΩresistor. Otherwise, it should be pulled low
			to ground with a 220-Ωresistor.
			Serial data. The TSB12LV26 determines whether a two-wire serial ROM is implemented at reset. If a two-wire
			serial ROM is detected, then this terminal provides the SDA serial data signaling. This terminal must be wired
SDA	5	I/O	low to indicate no serial ROM is present.
			This terminal is implemented as open-drain, and for normal operation (a ROM is implemented in the design),
			this terminal should be pulled high to the ROM VCC with a 2.7-kΩresistor. Otherwise, it should be pulled low
			to ground with a 220-Ωresistor.

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