3.5 Status Register

The status register provides status over the TSB12LV26 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification. See Table 3±4 for a complete description of the register contents.

Bit

15

 

14

13

 

12

 

11

10

 

9

8

 

7

 

6

5

4

 

3

 

2

 

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

 

Status

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RCU

 

RCU

RCU

 

RCU

RCU

R

 

R

RCU

 

R

 

R

 

R

 

R

 

R

 

R

 

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

 

0

 

0

0

 

1

0

 

0

 

0

0

1

 

0

 

0

 

0

0

 

 

Register:

Status

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read/Clear/Update, Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

06h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

0210h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 3±4. Status Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

 

FIELD NAME

 

TYPE

 

 

 

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

 

PAR_ERR

 

RCU

Detected parity error. This bit is set when a parity error is detected, either address or data parity errors.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Signaled system error. This bit is set when

 

 

 

 

is enabled and the TSB12LV26 has signaled a

14

 

SYS_ERR

 

RCU

PCI_SERR

 

 

system error to the host.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13

 

MABORT

 

RCU

Received master abort. This bit is set when a cycle initiated by the TSB12LV26 on the PCI bus has been

 

 

terminated by a master abort.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

 

TABORT_REC

 

RCU

Received target abort. This bit is set when a cycle initiated by the TSB12LV26 on the PCI bus was

 

 

terminated by a target abort.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

 

TABORT_SIG

 

RCU

Signaled target abort. This bit is set by the TSB12LV26 when it terminates a transaction on the PCI bus

 

 

with a target abort.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEVSEL timing. Bits 10±9 encode the timing of

 

 

 

 

and are hardwired to 01b indicating that

10±9

 

PCI_SPEED

 

R

 

PCI_DEVSEL

 

 

 

the TSB12LV26 asserts this signal at a medium speed on nonconfiguration cycle accesses.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data parity error detected. This bit is set when the following conditions have been met:

 

 

8

 

DATAPAR

 

RCU

 

a. PCI_PERR was asserted by any PCI device including the TSB12LV26.

 

 

 

 

 

 

 

b. The TSB12LV26 was the bus master during the data parity error.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

c. The parity error response bit is set in the PCI command register (offset 04h, see Section 3.4).

 

 

 

 

 

 

 

 

 

 

7

 

FBB_CAP

 

R

 

Fast back-to-back capable. The TSB12LV26 cannot accept fast back-to-back transactions; thus, this

 

 

 

bit is hardwired to 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

 

UDF

 

 

R

 

User definable features (UDF) supported. The TSB12LV26 does not support the UDF; thus, this bit is

 

 

 

 

hardwired to 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

66MHZ

 

 

R

 

66-MHz capable. The TSB12LV26 operates at a maximum PCI_CLK frequency of 33 MHz; therefore,

 

 

 

 

this bit is hardwired to 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

CAPLIST

 

R

 

Capabilities list. This bit returns 1 when read, indicating that capabilities additional to standard PCI are

 

 

 

implemented. The linked list of PCI power management capabilities is implemented in this function.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3±0

 

RSVD

 

 

R

 

Reserved. Bits 3±0 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3±5

Page 24 Page 26
Page 25
Image 25
Texas Instruments TSB12LV26 manual ±4. Status Register Description
Page 24 Page 26

TSB12LV26 specifications

The Texas Instruments TSB12LV26 is a high-performance, low-voltage transceiver designed for Serial Bus applications. It is widely recognized for its robust features and versatility, making it a popular choice among engineers and designers in various industries. One of the primary features of the TSB12LV26 is its support for high-speed data transmission, enabling it to operate at speeds up to 400 Mbps. This capability is essential for applications that demand rapid data transfer, such as in multimedia and communication systems.

The TSB12LV26 is part of the IEEE 1394 standard, also known as FireWire, which is widely used for connecting devices like digital cameras, external hard drives, and printers. The chip operates within a voltage range of 2.7V to 3.6V, making it suitable for low-power applications where energy efficiency is critical. The integration of advanced Low-Voltage Differential Signaling (LVDS) technology within the TSB12LV26 enhances signal integrity and reduces electromagnetic interference, resulting in more reliable performance over longer distances.

In terms of its physical characteristics, the TSB12LV26 is available in a compact 48-pin HTQFP package, which is beneficial for space-constrained designs. The device features a comprehensive set of input and output pins, allowing for flexible connectivity options. Additionally, the TSB12LV26 includes advanced power management features, including low-power modes that help extend battery life in portable devices.

Another significant advantage of the TSB12LV26 is its capability for peer-to-peer communication, enabling devices to connect and communicate directly without the need for a central controller. This functionality supports a wide range of device configurations and simplifies system architecture. Furthermore, the transceiver offers built-in support for asynchronous and isochronous data transfer, making it adaptable for various application requirements.

The TSB12LV26 also adheres to stringent EMI and ESD protection standards, ensuring reliable operation in challenging environments. With a rich feature set, excellent performance characteristics, and compliance with industry standards, the Texas Instruments TSB12LV26 remains an ideal choice for engineers looking to implement high-speed and reliable communication in their designs. Overall, it represents a significant advancement in the field of data transmission technology, making it a preferred component for numerous electronic applications.
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