Texas Instruments TSB12LV26 manual ±4. Status Register Description

3.5 Status Register

The status register provides status over the TSB12LV26 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification. See Table 3±4 for a complete description of the register contents.

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Status

Type

RCU

RCU

RCU

RCU

RCU

R

R

RCU

R

R

R

R

R

R

R

R

Default

0

0

0

0

0

0

1

0

0

0

0

1

0

0

0

0

Register:

Status

Type:

Read/Clear/Update, Read-only

Offset:

06h

Default:

0210h

Table 3±4. Status Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

15

PAR_ERR

RCU

Detected parity error. This bit is set when a parity error is detected, either address or data parity errors.

Signaled system error. This bit is set when

is enabled and the TSB12LV26 has signaled a

14

SYS_ERR

RCU

PCI_SERR

system error to the host.

13

MABORT

RCU

Received master abort. This bit is set when a cycle initiated by the TSB12LV26 on the PCI bus has been

terminated by a master abort.

12

TABORT_REC

RCU

Received target abort. This bit is set when a cycle initiated by the TSB12LV26 on the PCI bus was

terminated by a target abort.

11

TABORT_SIG

RCU

Signaled target abort. This bit is set by the TSB12LV26 when it terminates a transaction on the PCI bus

with a target abort.

DEVSEL timing. Bits 10±9 encode the timing of

and are hardwired to 01b indicating that

10±9

PCI_SPEED

R

PCI_DEVSEL

the TSB12LV26 asserts this signal at a medium speed on nonconfiguration cycle accesses.

Data parity error detected. This bit is set when the following conditions have been met:

8

DATAPAR

RCU

a. PCI_PERR was asserted by any PCI device including the TSB12LV26.

b. The TSB12LV26 was the bus master during the data parity error.

c. The parity error response bit is set in the PCI command register (offset 04h, see Section 3.4).

7

FBB_CAP

R

Fast back-to-back capable. The TSB12LV26 cannot accept fast back-to-back transactions; thus, this

bit is hardwired to 0.

6

UDF

R

User definable features (UDF) supported. The TSB12LV26 does not support the UDF; thus, this bit is

hardwired to 0.

5

66MHZ

R

66-MHz capable. The TSB12LV26 operates at a maximum PCI_CLK frequency of 33 MHz; therefore,

this bit is hardwired to 0.

4

CAPLIST

R

Capabilities list. This bit returns 1 when read, indicating that capabilities additional to standard PCI are

implemented. The linked list of PCI power management capabilities is implemented in this function.

3±0

RSVD

R

Reserved. Bits 3±0 return 0s when read.

3±5