4.22 Interrupt Mask Register

The interrupt mask set/clear register is used to enable the various TSB12LV26 interrupt sources. Reads from either the set register or the clear register always return the contents of the interrupt mask register. In all cases except masterIntEnable (bit 31) and VendorSpecific (bit 30), the enables for each interrupt event align with the interrupt event register bits detailed in Table 4±14. See Table 4±15 for a description of bits 31 and 30.

This register is fully compliant with OHCI and the TSB12LV26 adds an OHCI 1.0 compliant interrupt function to bit 30.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

Interrupt mask

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RSCU

RSC

R

R

R

RSCU

RSCU

RSCU

RSCU

RSCU

RSCU

RSCU

RSCU

R

RSCU

RSCU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

X

X

0

0

0

X

X

X

X

X

X

X

X

0

X

X

Bit

15

 

14

13

12

11

 

10

 

9

8

 

7

6

5

 

4

3

2

1

0

Name

 

 

 

 

 

 

 

 

 

 

 

 

Interrupt mask

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

 

R

R

 

R

 

R

 

RSCU

RSCU

 

RU

RU

RSCU

 

RSCU

RSCU

RSCU

RSCU

RSCU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

0

 

0

 

0

 

X

X

 

X

X

X

 

X

X

X

X

X

 

Register:

 

Interrupt mask

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only

 

 

 

 

Offset:

 

88h

 

set register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8Ch

 

clear register

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

XXXX 0XXXh

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 4±15. Interrupt Mask Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

FIELD NAME

 

TYPE

 

 

 

 

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Master interrupt enable. If this bit is set, then external interrupts are generated in accordance with the

31

masterIntEnable

 

RSCU

 

interrupt mask register. If this bit is cleared, then external interrupts are not generated regardless of the

 

 

 

 

 

 

 

 

interrupt mask register settings.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

30

vendorSpecific

 

RSC

 

When this bit is set, this vendor-specific interrupt mask enables interrupt generation when bit 30

 

 

(vendorSpecific) of the interrupt event register (OHCI offset 80h/84h, see Section 4.21) is set.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

29±0

 

 

 

 

 

 

 

See Table 4±14.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4±19

Page 56 Page 58
Page 57
Image 57
Texas Instruments TSB12LV26 manual Interrupt mask, ±15. Interrupt Mask Register Description, Rscu RSC
Page 56 Page 58

TSB12LV26 specifications

The Texas Instruments TSB12LV26 is a high-performance, low-voltage transceiver designed for Serial Bus applications. It is widely recognized for its robust features and versatility, making it a popular choice among engineers and designers in various industries. One of the primary features of the TSB12LV26 is its support for high-speed data transmission, enabling it to operate at speeds up to 400 Mbps. This capability is essential for applications that demand rapid data transfer, such as in multimedia and communication systems.

The TSB12LV26 is part of the IEEE 1394 standard, also known as FireWire, which is widely used for connecting devices like digital cameras, external hard drives, and printers. The chip operates within a voltage range of 2.7V to 3.6V, making it suitable for low-power applications where energy efficiency is critical. The integration of advanced Low-Voltage Differential Signaling (LVDS) technology within the TSB12LV26 enhances signal integrity and reduces electromagnetic interference, resulting in more reliable performance over longer distances.

In terms of its physical characteristics, the TSB12LV26 is available in a compact 48-pin HTQFP package, which is beneficial for space-constrained designs. The device features a comprehensive set of input and output pins, allowing for flexible connectivity options. Additionally, the TSB12LV26 includes advanced power management features, including low-power modes that help extend battery life in portable devices.

Another significant advantage of the TSB12LV26 is its capability for peer-to-peer communication, enabling devices to connect and communicate directly without the need for a central controller. This functionality supports a wide range of device configurations and simplifies system architecture. Furthermore, the transceiver offers built-in support for asynchronous and isochronous data transfer, making it adaptable for various application requirements.

The TSB12LV26 also adheres to stringent EMI and ESD protection standards, ensuring reliable operation in challenging environments. With a rich feature set, excellent performance characteristics, and compliance with industry standards, the Texas Instruments TSB12LV26 remains an ideal choice for engineers looking to implement high-speed and reliable communication in their designs. Overall, it represents a significant advancement in the field of data transmission technology, making it a preferred component for numerous electronic applications.
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