CY62158E MoBL→
Switching Characteristics
Over the Operating Range [9]
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| 45 ns | Unit | |
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| Min |
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Read Cycle |
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tRC |
| Read Cycle Time |
| 45 |
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| ns | ||||
tAA |
| Address to Data Valid |
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| 45 | ns | |||||
tOHA |
| Data Hold from Address Change | 10 |
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| ns | |||||
tACE |
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| 1 LOW and CE2 HIGH to Data Valid |
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| 45 | ns | ||||
CE |
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tDOE |
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| LOW to Data Valid |
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| 22 | ns | ||
OE |
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t |
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| LOW to Low Z [10] | 5 |
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| ns | ||
OE |
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LZOE |
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t |
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| HIGH to High Z [10, 11] |
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| 18 | ns | ||
OE |
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HZOE |
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t |
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| LOW and CE | HIGH to Low Z [10] | 10 |
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CE | 1 |
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LZCE |
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| 2 |
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t |
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| HIGH or CE | LOW to High Z [10, 11] |
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| 18 | ns |
CE | 1 |
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HZCE |
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| 2 |
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tPU |
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| 1 LOW and CE2 HIGH to Power Up | 0 |
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CE |
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tPD |
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| 1 HIGH or CE2 LOW to Power Down |
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| 45 | ns | ||||
CE |
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Write Cycle [12] |
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tWC |
| Write Cycle Time |
| 45 |
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tSCE |
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| 1 LOW and CE2 HIGH to Write End | 35 |
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| ns | ||||
CE |
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tAW |
| Address Setup to Write End | 35 |
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tHA |
| Address Hold from Write End | 0 |
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tSA |
| Address Setup to Write Start | 0 |
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tPWE |
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| Pulse Width |
| 35 |
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| ns | |
WE |
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tSD |
| Data Setup to Write End | 25 |
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tHD |
| Data Hold from Write End | 0 |
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t |
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| LOW to High Z [10, 11] |
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| 18 | ns | ||
WE |
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HZWE |
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t |
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| HIGH to Low Z [10] | 10 |
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| ns | ||
WE |
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LZWE |
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Notes
9.Test conditions for all parameters other than
10.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
11.tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state.
12.The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
Document #: | Page 5 of 10 |
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