Cypress CY62147DV18 Data Retention Waveform, Switching Characteristics Over the Operating Range

			CY62147DV18
			MoBL2™
Data Retention Waveform[9]
wqewqewq
	VCC(min)	DATA RETENTION MODE	VCC(min)
VCC		VDR > 1.0 V
CE or	tCDR		tR
BHE.BLE

Switching Characteristics Over the Operating Range [10.]

						55 ns			70 ns
Parameter					Description	Min.	Max.	Min.		Max.	Unit
Read Cycle
tRC	Read Cycle Time					55		70			ns
tAA	Address to Data Valid						55			70	ns
tOHA	Data Hold from Address Change					10		10			ns
tACE	CE	LOW to Data Valid					55			70	ns
tDOE	OE	LOW to Data Valid					25			35	ns
tLZOE	OE	LOW to LOW Z[11]				5		5			ns
tHZOE	OE	HIGH to High Z[11, 12]					16			16	ns
tLZCE	CE	LOW to Low Z[11]				10		10			ns
tHZCE	CE	HIGH to High Z[11, 12]					20			25	ns
tPU	CE	LOW to Power-Up				0		0			ns
tPD	CE	HIGH to Power-Down					55			70	ns
tDBE	BLE		/	BHE	LOW to Data Valid		55			70	ns
tLZBE	BLE		/	BHE	LOW to Low Z[11]	10		10			ns
tHZBE	BLE		/	BHE	HIGH to HIGH Z[11, 12]		20			25	ns
Write Cycle[13]
tWC	Write Cycle Time					55		70			ns
tSCE	CE	LOW to Write End				40		50			ns
tAW	Address Set-up to Write End					40		50			ns
tHA	Address Hold from Write End					0		0			ns
tSA	Address Set-up to Write Start					0		0			ns
tPWE	WE	Pulse Width				40		45			ns
tBW	BLE		/	BHE	LOW to Write End	40		50			ns
tSD	Data Set-Up to Write End					25		30			ns
tHD	Data Hold from Write End					0		0			ns
tHZWE	WE	LOW to High-Z[11,12]					20			25	ns
tLZWE	WE	HIGH to Low-Z[11]				10		10			ns

Notes:

9.BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signal or by disabling both BHE and BLE.

10.Test conditions for all parameters other than three-state parameters assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.

11.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

12.tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state.

13.The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.

Document #: 38-05343 Rev. *B Page 5 of 11

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